91227e2f61
Removes memory accesses to constant values and replaces them with mov instructions. This would allow this library to be compatible with execute-only memory layouts. Bug: 124323156 Test: poc Change-Id: I801d4cfff953b9d13b80a97be04a3223117df29f
231 lines
6.4 KiB
ArmAsm
231 lines
6.4 KiB
ArmAsm
.macro push_v_regs
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stp q8, q9, [sp, #-32]!
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stp q10, q11, [sp, #-32]!
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stp q12, q13, [sp, #-32]!
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stp q14, q15, [sp, #-32]!
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stp X8, X9, [sp, #-16]!
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stp X10, X11, [sp, #-16]!
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stp X12, X13, [sp, #-16]!
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stp X14, X15, [sp, #-16]!
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stp X16, X17, [sp, #-16]!
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stp X18, X19, [sp, #-16]!
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stp X20, X21, [sp, #-16]!
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stp X29, X30, [sp, #-16]!
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.endm
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.macro pop_v_regs
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ldp X29, X30, [sp], #16
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ldp X20, X21, [sp], #16
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ldp X18, X19, [sp], #16
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ldp X16, X17, [sp], #16
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ldp X14, X15, [sp], #16
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ldp X12, X13, [sp], #16
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ldp X10, X11, [sp], #16
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ldp X8, X9, [sp], #16
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ldp q14, q15, [sp], #32
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ldp q12, q13, [sp], #32
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ldp q10, q11, [sp], #32
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ldp q8, q9, [sp], #32
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.endm
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.text
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.p2align 2
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.global ixheaacd_cos_sin_mod_loop1
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ixheaacd_cos_sin_mod_loop1:
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// STMFD sp!, {x4-x12, x14}
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push_v_regs
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//stp x19, x20,[sp,#-16]!
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//VPUSH {D8-D11}
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//generating load addresses
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ADD x4, x0, x1, lsl #3 //psubband1
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SUB x4, x4, #4
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ADD x5, x3, x1, lsl #3 //psubband1_t
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SUB x5, x5, #8
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ASR x6, x1, #2
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MOV w19, #0
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DUP V0.8h, w19
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LOOP1:
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//first part
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ld1 {v0.h}[0] , [x2]
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ADD x2, x2, #2
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ld1 {v0.h}[2] , [x2]
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ADD x2, x2, #2
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rev64 v1.2s, v0.2s
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ld1 {v2.s}[0], [x0]
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ADD x0, x0, #4
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ADD x7, x0, #252
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ld1 {v2.s}[1], [x7]
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ld1 {v3.s}[0], [x4]
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ADD x7, x4, #256
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ld1 {v3.s}[1], [x7]
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SUB x4, x4, #4
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sMULL v4.2d, v0.2s, v2.2s //qsub 2nd
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sshr v4.2d, v4.2d, #16
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sMULL v6.2d, v0.2s, v3.2s //add 2nd
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sshr v6.2d, v6.2d, #16
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sMULL v8.2d, v1.2s, v2.2s //add 1st
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sshr v8.2d, v8.2d, #16
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sMULL v10.2d, v1.2s, v3.2s //qsub 1st
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sshr v10.2d, v10.2d, #16
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add v0.4s, v8.4s , v6.4s
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SQSUB v2.4s, v10.4s , v4.4s
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//shrn v0.2s, v0.2d,#32
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//shrn v2.2s, v2.2d,#32
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mov v3.16b, v0.16b
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mov v1.16b, v2.16b
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ST2 {v0.s, v1.s}[0], [x3]
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ADD x3, x3, #8
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ADD x7, x3, #248
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ST2 {v2.s, v3.s}[2], [x7]
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MOV w19, #0
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DUP V0.8h, w19
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//second part
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ld1 {v0.h}[0] , [x2]
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ADD x2, x2, #2
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ld1 {v0.h}[2] , [x2]
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ADD x2, x2, #2
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rev64 v1.2s, v0.2s
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ld1 {v2.s}[0], [x0]
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ADD x0, x0, #4
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ADD x7, x0, #252
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ld1 {v2.s}[1], [x7]
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ld1 {v3.s}[0], [x4]
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ADD x7, x4, #256
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ld1 {v3.s}[1], [x7]
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SUB x4, x4, #4
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sMULL v4.2d, v0.2s, v2.2s //qsub 2nd
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sshr v4.2d, v4.2d, #16
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sMULL v6.2d, v0.2s, v3.2s //add 2nd
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sshr v6.2d, v6.2d, #16
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sMULL v8.2d, v1.2s, v2.2s //add 1st
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sshr v8.2d, v8.2d, #16
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sMULL v10.2d, v1.2s, v3.2s //qsub 1st
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sshr v10.2d, v10.2d, #16
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ADD v0.4s, v10.4s , v4.4s
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SQSUB v2.4s, v8.4s , v6.4s
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//shrn v0.2s, v0.2d,#32
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//shrn v2.2s, v2.2d,#32
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mov v3.16b, v0.16b
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mov v1.16b, v2.16b
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ST2 {v0.s, v1.s}[0], [x5]
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ADD x7, x5, #256
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ST2 {v2.s, v3.s}[2], [x7]
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SUB x5, x5, #8
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MOV w19, #0
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DUP V0.8h, w19
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//Third part
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ld1 {v0.h}[0] , [x2]
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ADD x2, x2, #2
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ld1 {v0.h}[2] , [x2]
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ADD x2, x2, #2
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rev64 v1.2s, v0.2s
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ld1 {v2.s}[0], [x0], #4
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ADD x7, x0, #252
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ld1 {v2.s}[1], [x7]
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ld1 {v3.s}[0], [x4]
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ADD x7, x4, #256
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ld1 {v3.s}[1], [x7]
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SUB x4, x4, #4
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sMULL v4.2d, v0.2s, v2.2s //qsub 2nd
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sshr v4.2d, v4.2d, #16
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sMULL v6.2d, v0.2s, v3.2s //add 2nd
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sshr v6.2d, v6.2d, #16
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sMULL v8.2d, v1.2s, v2.2s //add 1st
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sshr v8.2d, v8.2d, #16
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sMULL v10.2d, v1.2s, v3.2s //qsub 1st
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sshr v10.2d, v10.2d, #16
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add v0.4s, v8.4s , v6.4s
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SQSUB v2.4s, v10.4s , v4.4s
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//shrn v0.2s, v0.2d,#32
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//shrn v2.2s, v2.2d,#32
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mov v3.16b, v0.16b
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mov v1.16b, v2.16b
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ST2 {v0.s, v1.s}[0], [x3]
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ADD x3, x3, #8
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ADD x7, x3, #248
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ST2 {v2.s, v3.s}[2], [x7]
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MOV w19, #0
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DUP V0.8h, w19
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//Fourth part
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ld1 {v0.h}[0] , [x2]
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ADD x2, x2, #2
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ld1 {v0.h}[2] , [x2]
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ADD x2, x2, #2
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rev64 v1.2s, v0.2s
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ld1 {v2.s}[0], [x0]
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ADD x0, x0, #4
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ADD x7, x0, #252
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ld1 {v2.s}[1], [x7]
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ld1 {v3.s}[0], [x4]
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ADD x7, x4, #256
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ld1 {v3.s}[1], [x7]
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SUB x4, x4, #4
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sMULL v4.2d, v0.2s, v2.2s //qsub 2nd
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sshr v4.2d, v4.2d, #16
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sMULL v6.2d, v0.2s, v3.2s //add 2nd
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sshr v6.2d, v6.2d, #16
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sMULL v8.2d, v1.2s, v2.2s //add 1st
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sshr v8.2d, v8.2d, #16
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sMULL v10.2d, v1.2s, v3.2s //qsub 1st
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sshr v10.2d, v10.2d, #16
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ADD v0.4s, v10.4s , v4.4s
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SQSUB v2.4s, v8.4s , v6.4s
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//shrn v0.2s, v0.2d,#32
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//shrn v2.2s, v2.2d,#32
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mov v3.16b, v0.16b
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mov v1.16b, v2.16b
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ST2 {v0.s, v1.s}[0], [x5]
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ADD x7, x5, #256
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SUBS x6, x6, #1
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ST2 {v2.s, v3.s}[2], [x7]
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SUB x5, x5, #8
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MOV w19, #0
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DUP V0.8h, w19
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BGT LOOP1
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//VPOP {D8-D11}
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// LDMFD sp!, {x4-x12, x15}
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//ldp x19, x20,[sp],#16
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pop_v_regs
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ret
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