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Properly mark the type for ARM assembly functions. am: 331810f057

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Original change: 1414133

Change-Id: Ice88af6abbaec9ae277a56fcf7df516ba2e9486f
This commit is contained in:
Stephen Hines 2020-08-28 18:32:16 +00:00 • committed by Automerger Merge Worker
commit 924a4628e0
22 changed files with 22 additions and 0 deletions
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1
decoder/armv7/ixheaacd_complex_fft_p2.s
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@ -1,6 +1,7 @@
.text
.p2align 2
.global ixheaacd_complex_fft_p2_asm
.type ixheaacd_complex_fft_p2_asm, %function
ixheaacd_complex_fft_p2_asm:
STMFD sp!, {r0-r12, lr}

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decoder/armv7/ixheaacd_complex_ifft_p2.s
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@ -1,6 +1,7 @@
.text
.p2align 2
.global ixheaacd_complex_ifft_p2_asm
.type ixheaacd_complex_ifft_p2_asm, %function
ixheaacd_complex_ifft_p2_asm:
STMFD sp!, {r0-r12, lr}

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decoder/armv7/ixheaacd_dct3_32.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_dct3_32
.type ixheaacd_dct3_32, %function
.extern ixheaacd_radix4bfly
.hidden ixheaacd_radix4bfly
.extern ixheaacd_postradixcompute4

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decoder/armv7/ixheaacd_dec_DCT2_64_asm.s
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@ -29,6 +29,7 @@
.hidden ixheaacd_sbr_imdct_using_fft
.global ixheaacd_dec_DCT2_64_asm
.type ixheaacd_dec_DCT2_64_asm, %function
ixheaacd_dec_DCT2_64_asm:

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decoder/armv7/ixheaacd_esbr_cos_sin_mod_loop1.s
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@ -23,6 +23,7 @@
.p2align 2
.global ixheaacd_esbr_cos_sin_mod_loop1
.type ixheaacd_esbr_cos_sin_mod_loop1, %function
ixheaacd_esbr_cos_sin_mod_loop1:
STMFD sp!, {r4-r12, r14}

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decoder/armv7/ixheaacd_esbr_cos_sin_mod_loop2.s
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@ -23,6 +23,7 @@
.p2align 2
.global ixheaacd_esbr_cos_sin_mod_loop2
.type ixheaacd_esbr_cos_sin_mod_loop2, %function
ixheaacd_esbr_cos_sin_mod_loop2:
STMFD sp!, {r4-r12, r14}

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decoder/armv7/ixheaacd_esbr_fwd_modulation.s
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@ -24,6 +24,7 @@
.extern ixheaacd_esbr_cos_sin_mod
.hidden ixheaacd_esbr_cos_sin_mod
.global ixheaacd_esbr_fwd_modulation
.type ixheaacd_esbr_fwd_modulation, %function
ixheaacd_esbr_fwd_modulation:
STMFD sp!, {r4-r12, lr}

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decoder/armv7/ixheaacd_esbr_qmfsyn64_winadd.s
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@ -13,6 +13,7 @@
.text
.p2align 2
.global ixheaacd_esbr_qmfsyn64_winadd
.type ixheaacd_esbr_qmfsyn64_winadd, %function
ixheaacd_esbr_qmfsyn64_winadd: @ PROC

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decoder/armv7/ixheaacd_esbr_radix4bfly.s
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@ -20,6 +20,7 @@
.global ixheaacd_esbr_radix4bfly
.type ixheaacd_esbr_radix4bfly, %function
ixheaacd_esbr_radix4bfly:

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decoder/armv7/ixheaacd_fwd_modulation.s
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@ -24,6 +24,7 @@
.extern ixheaacd_cos_sin_mod
.hidden ixheaacd_cos_sin_mod
.global ixheaacd_fwd_modulation
.type ixheaacd_fwd_modulation, %function
ixheaacd_fwd_modulation:
STMFD sp!, {r3-r9, r12, lr}

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decoder/armv7/ixheaacd_mps_complex_fft_64_asm.s
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@ -1,6 +1,7 @@
.text
.p2align 2
.global ixheaacd_mps_complex_fft_64_asm
.type ixheaacd_mps_complex_fft_64_asm, %function
ixheaacd_mps_complex_fft_64_asm:
@LDR r4,[sp]

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decoder/armv7/ixheaacd_post_radix_compute2.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_postradixcompute2
.type ixheaacd_postradixcompute2, %function
ixheaacd_postradixcompute2:

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decoder/armv7/ixheaacd_post_radix_compute4.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_postradixcompute4
.type ixheaacd_postradixcompute4, %function
ixheaacd_postradixcompute4:

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decoder/armv7/ixheaacd_radix4_bfly.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_radix4bfly
.type ixheaacd_radix4bfly, %function
ixheaacd_radix4bfly:

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decoder/armv7/ixheaacd_sbr_imdct_using_fft.s
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@ -23,6 +23,7 @@
.p2align 2
.global ixheaacd_sbr_imdct_using_fft
.type ixheaacd_sbr_imdct_using_fft, %function
ixheaacd_sbr_imdct_using_fft:
STMFD sp!, {r4-r12, lr}

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decoder/armv7/ixheaacd_sbr_qmfanal32_winadds.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_sbr_qmfanal32_winadds
.type ixheaacd_sbr_qmfanal32_winadds, %function
ixheaacd_sbr_qmfanal32_winadds:

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decoder/armv7/ixheaacd_sbr_qmfanal32_winadds_eld.s
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@ -1,6 +1,7 @@
.text
.p2align 2
.global ixheaacd_sbr_qmfanal32_winadds_eld
.type ixheaacd_sbr_qmfanal32_winadds_eld, %function
ixheaacd_sbr_qmfanal32_winadds_eld:

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decoder/armv7/ixheaacd_sbr_qmfsyn64_winadd.s
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@ -22,6 +22,7 @@
.text
.p2align 2
.global ixheaacd_sbr_qmfsyn64_winadd
.type ixheaacd_sbr_qmfsyn64_winadd, %function
ixheaacd_sbr_qmfsyn64_winadd:

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decoder/armv7/ixheaacd_shiftrountine.s
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@ -25,6 +25,7 @@
.text
.p2align 2
.global ixheaacd_shiftrountine
.type ixheaacd_shiftrountine, %function
ixheaacd_shiftrountine:
CMP r3, #0
STMFD sp!, {r4-r7, r12}

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decoder/armv7/ixheaacd_shiftrountine_with_rnd_eld.s
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@ -1,6 +1,7 @@
.text
.p2align 2
.global ixheaacd_shiftrountine_with_rnd_eld
.type ixheaacd_shiftrountine_with_rnd_eld, %function
ixheaacd_shiftrountine_with_rnd_eld:
STMFD sp!, {r4-r12, r14}

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decoder/armv7/ixheaacd_shiftrountine_with_round.s
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@ -25,6 +25,7 @@
.text
.p2align 2
.global ixheaacd_shiftrountine_with_rnd
.type ixheaacd_shiftrountine_with_rnd, %function
ixheaacd_shiftrountine_with_rnd:
STMFD sp!, {r4-r12, r14}
MOV r4, #0x1f

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decoder/armv7/ixheaacd_shiftrountine_with_round_hq.s
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@ -4,6 +4,7 @@
.text
.p2align 2
.global ixheaacd_shiftrountine_with_rnd_hq
.type ixheaacd_shiftrountine_with_rnd_hq, %function
ixheaacd_shiftrountine_with_rnd_hq:
STMFD sp!, {r4-r12, r14}