diff --git a/Android.bp b/Android.bp index f10e600..10def9e 100644 --- a/Android.bp +++ b/Android.bp @@ -95,6 +95,7 @@ cc_library_static { "decoder/ixheaacd_mps_temp_process.c", "decoder/ixheaacd_mps_temp_reshape.c", "decoder/ixheaacd_pns_js_thumb.c", + "decoder/ixheaacd_peak_limiter.c", "decoder/ixheaacd_pred_vec_block.c", "decoder/ixheaacd_process.c", "decoder/ixheaacd_ps_bitdec.c", diff --git a/CMakeLists.txt b/CMakeLists.txt index 471681e..813b9d3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -85,6 +85,7 @@ list( "${XAAC_ROOT}/decoder/ixheaacd_mps_temp_process.c" "${XAAC_ROOT}/decoder/ixheaacd_mps_temp_reshape.c" "${XAAC_ROOT}/decoder/ixheaacd_pns_js_thumb.c" + "${XAAC_ROOT}/decoder/ixheaacd_peak_limiter.c" "${XAAC_ROOT}/decoder/ixheaacd_pred_vec_block.c" "${XAAC_ROOT}/decoder/ixheaacd_process.c" "${XAAC_ROOT}/decoder/ixheaacd_ps_bitdec.c" diff --git a/decoder/armv7/ixheaacd_function_selector_arm_non_neon.c b/decoder/armv7/ixheaacd_function_selector_arm_non_neon.c index 75ca6b3..d15cf74 100644 --- a/decoder/armv7/ixheaacd_function_selector_arm_non_neon.c +++ b/decoder/armv7/ixheaacd_function_selector_arm_non_neon.c @@ -69,7 +69,7 @@ VOID(*ixheaacd_covariance_matrix_calc_2) WORD16) = &ixheaacd_covariance_matrix_calc_2_armv7; VOID(*ixheaacd_over_lap_add1) -(WORD32 *, WORD32 *, WORD16 *, const WORD16 *, WORD16, WORD16, +(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16) = &ixheaacd_over_lap_add1_dec; VOID(*ixheaacd_over_lap_add2) @@ -155,13 +155,13 @@ VOID(*ixheaacd_post_twiddle) WORD npoints) = &ixheaacd_post_twiddle_dec; VOID(*ixheaacd_post_twid_overlap_add) -(WORD16 pcm_out[], WORD32 spec_data[], +(WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) = &ixheaacd_post_twid_overlap_add_dec; VOID(*ixheaacd_neg_shift_spec) -(WORD32 *coef, WORD16 *out, WORD16 q_shift, +(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) = &ixheaacd_neg_shift_spec_dec; VOID(*ixheaacd_spec_to_overlapbuf) @@ -169,7 +169,7 @@ VOID(*ixheaacd_spec_to_overlapbuf) WORD32 size) = &ixheaacd_spec_to_overlapbuf_armv7; VOID(*ixheaacd_overlap_buf_out) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) = &ixheaacd_overlap_buf_out_armv7; VOID(*ixheaacd_overlap_out_copy) diff --git a/decoder/armv7/ixheaacd_function_selector_armv7.c b/decoder/armv7/ixheaacd_function_selector_armv7.c index c9f41f9..a96063c 100644 --- a/decoder/armv7/ixheaacd_function_selector_armv7.c +++ b/decoder/armv7/ixheaacd_function_selector_armv7.c @@ -76,7 +76,7 @@ VOID(*ixheaacd_covariance_matrix_calc_2) WORD16) = &ixheaacd_covariance_matrix_calc_2_armv7; VOID(*ixheaacd_over_lap_add1) -(WORD32 *, WORD32 *, WORD16 *, const WORD16 *, WORD16, WORD16, +(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16) = &ixheaacd_over_lap_add1_armv7; VOID(*ixheaacd_over_lap_add2) @@ -161,12 +161,13 @@ VOID(*ixheaacd_post_twiddle) WORD npoints) = &ixheaacd_post_twiddle_armv7; VOID(*ixheaacd_post_twid_overlap_add) -(WORD16 pcm_out[], WORD32 spec_data[], +(WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) = &ixheaacd_post_twid_overlap_add_armv7; + VOID(*ixheaacd_neg_shift_spec) -(WORD32 *coef, WORD16 *out, WORD16 q_shift, +(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) = &ixheaacd_neg_shift_spec_armv7; VOID(*ixheaacd_spec_to_overlapbuf) @@ -174,11 +175,11 @@ VOID(*ixheaacd_spec_to_overlapbuf) WORD32 size) = &ixheaacd_spec_to_overlapbuf_armv7; VOID(*ixheaacd_overlap_buf_out) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) = &ixheaacd_overlap_buf_out_armv7; VOID(*ixheaacd_overlap_out_copy) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac) = &ixheaacd_overlap_out_copy_armv7; VOID(*ixheaacd_pretwiddle_compute) diff --git a/decoder/armv7/ixheaacd_lap1.s b/decoder/armv7/ixheaacd_lap1.s index 999dd35..2f2ced3 100644 --- a/decoder/armv7/ixheaacd_lap1.s +++ b/decoder/armv7/ixheaacd_lap1.s @@ -29,7 +29,7 @@ ixheaacd_overlap_buf_out_armv7: STMFD sp!, {r4-r5} - MOV r3, r3, lsl #1 + MOV r3, r3, lsl #2 OUTSAMPLE_LOOP: @@ -37,11 +37,11 @@ OUTSAMPLE_LOOP: LDR r5, [r1], #4 SUBS r2, r2, #2 - QADD16 r4, r4, r4 - QADD16 r5, r5, r5 + LSL r4,r4,#15 + LSL r5,r5,#15 - STRH r4, [r0], r3 - STRH r5, [r0], r3 + STR r4, [r0], r3 + STR r5, [r0], r3 BGT OUTSAMPLE_LOOP @@ -54,7 +54,7 @@ ixheaacd_overlap_out_copy_armv7: STMFD sp!, {r4-r9, r14} MOV r9, #32 MOV r8, r1 - MOV r3, r3, LSL #1 + MOV r3, r3, LSL #2 OUT_OVERLAP_LOOP: @@ -62,14 +62,14 @@ OUT_OVERLAP_LOOP: LDR r5, [r1], #4 SUBS r9, r9, #1 - QADD16 r4, r4, r4 - QADD16 r5, r5, r5 + LSL r4,r4,#15 + LSL r5,r5,#15 LDR r6, [r2], #4 LDR r7, [r2], #4 - STRH r4, [r0], r3 - STRH r5, [r0], r3 + STR r4, [r0], r3 + STR r5, [r0], r3 STR r6, [r8], #4 STR r7, [r8], #4 diff --git a/decoder/armv7/ixheaacd_no_lap1.s b/decoder/armv7/ixheaacd_no_lap1.s index 2884191..944e32b 100644 --- a/decoder/armv7/ixheaacd_no_lap1.s +++ b/decoder/armv7/ixheaacd_no_lap1.s @@ -32,79 +32,60 @@ ixheaacd_neg_shift_spec_armv7: ADD R6, R6, R0 MOV R8, #-16 SUB R6, R6, #12 - MOV R7, R3, LSL #1 + MOV R7, R3, LSL #2 VDUP.32 Q1, R2 - MOV R4, #0x8000 - VDUP.32 Q2, R4 - VLD1.32 {D0, D1}, [R6], R8 VQNEG.S32 Q0, Q0 VLD1.32 {D6, D7}, [R6], R8 VQSHL.S32 Q15, Q0, Q1 - VQADD.S32 Q14, Q15, Q2 - VSHR.S32 Q13, Q14, #16 - VREV64.32 Q13, Q13 + VMOV Q13, Q15 SUB R5, R5, #8 - VUZP.16 D27, D26 VQNEG.S32 Q3, Q3 - + VREV64.32 Q13,Q13 LOOP_1: - - VST1.16 D27[0], [R1], R7 - VQSHL.S32 Q12, Q3, Q1 - VLD1.32 {D0, D1}, [R6], R8 - VST1.16 D27[1], [R1], R7 - VQADD.S32 Q11, Q12, Q2 - VST1.16 D27[2], [R1], R7 - VQNEG.S32 Q0, Q0 - VST1.16 D27[3], [R1], R7 - VSHR.S32 Q10, Q11, #16 - VREV64.32 Q10, Q10 - SUBS R5, R5, #8 + VST1.32 {D27[0]},[R1], R7 + VQSHL.S32 Q12, Q3, Q1 + VLD1.32 {D0, D1}, [R6], R8 + VST1.32 {D27[1]}, [R1], R7 + VST1.32 {D26[0]}, [R1], R7 + VQNEG.S32 Q0, Q0 + VST1.32 {D26[1]}, [R1], R7 + VMOV Q10 , Q12 + SUBS R5, R5, #8 - VUZP.16 D21, D20 - VQSHL.S32 Q15, Q0, Q1 - VST1.16 D21[0], [R1], R7 - VLD1.32 {D6, D7}, [R6], R8 - VQADD.S32 Q14, Q15, Q2 - VST1.16 D21[1], [R1], R7 - VSHR.S32 Q13, Q14, #16 - VST1.16 D21[2], [R1], R7 - VREV64.32 Q13, Q13 - VST1.16 D21[3], [R1], R7 + VREV64.32 Q10,Q10 + VQSHL.S32 Q15, Q0, Q1 + VST1.32 {D21[0]},[R1], R7 + VLD1.32 {D6, D7}, [R6],R8 + VST1.32 {D21[1]}, [R1],R7 + VMOV Q13,Q15 + VST1.32 {D20[0]}, [R1],R7 + VST1.32 {D20[1]}, [R1],R7 + VREV64.32 Q13,Q13 + VQNEG.S32 Q3, Q3 - VUZP.16 D27, D26 - VQNEG.S32 Q3, Q3 + BGT LOOP_1 + VST1.32 {D27[0]},[R1],R7 + VQSHL.S32 Q12, Q3, Q1 + VST1.32 {D27[1]}, [R1],R7 + VST1.32 {D26[0]}, [R1],R7 + VST1.32 {D26[1]}, [R1],R7 + VMOV Q10, Q12 - - BGT LOOP_1 - - VST1.16 D27[0], [R1], R7 - VQSHL.S32 Q12, Q3, Q1 - VST1.16 D27[1], [R1], R7 - VST1.16 D27[2], [R1], R7 - VQADD.S32 Q11, Q12, Q2 - VST1.16 D27[3], [R1], R7 - VSHR.S32 Q10, Q11, #16 - - - VREV64.32 Q10, Q10 - - VUZP.16 D21, D20 - - VST1.16 D21[0], [R1], R7 - VST1.16 D21[1], [R1], R7 - VST1.16 D21[2], [R1], R7 - VST1.16 D21[3], [R1], R7 - VPOP {D8 - D15} - LDMFD sp!, {R4-R12, R15} + VREV64.32 Q10,Q10 + VST1.32 {D21[0]}, [R1], R7 + VST1.32 {D21[1]}, [R1], R7 + VST1.32 {D20[0]}, [R1], R7 + VST1.32 {D20[1]}, [R1], R7 + VPOP {D8 - D15} + LDMFD sp!, {R4-R12, R15} .end diff --git a/decoder/armv7/ixheaacd_overlap_add1.s b/decoder/armv7/ixheaacd_overlap_add1.s index b376470..5c8f3c4 100644 --- a/decoder/armv7/ixheaacd_overlap_add1.s +++ b/decoder/armv7/ixheaacd_overlap_add1.s @@ -32,6 +32,8 @@ ixheaacd_over_lap_add1_armv7: LDR R4, [SP, #104] LDR R5, [SP, #108] LDR R6, [SP, #112] + + LSL R6 , R6 , #1 MOV R10, R5, LSL #1 SUB R11, R10, #1 MOV R10, R11, LSL #2 @@ -45,11 +47,10 @@ ixheaacd_over_lap_add1_armv7: MOV R12, #-16 VDUP.16 Q11, R4 VLD1.32 {D6, D7}, [R10], R12 - MOV R7, #0x2000 + MOV R7, #0x0 VREV64.32 Q3, Q3 RSB R7, R7, #0 VQNEG.S32 Q0, Q3 - VDUP.32 Q10, R7 VUZP.16 D1, D0 SUB R11, R5, #1 VUZP.16 D7, D6 @@ -66,7 +67,6 @@ ixheaacd_over_lap_add1_armv7: ADD R6, R6, R2 - VMULL.U16 Q15, D7, D2 VLD1.32 {D4, D5}, [R1]! VSHR.U32 Q15, Q15, #16 @@ -81,12 +81,7 @@ ixheaacd_over_lap_add1_armv7: VQMOVN.S64 D28, Q13 VMULL.S32 Q13, D5, D15 VQMOVN.S64 D29, Q13 - - VQADD.S32 Q14, Q14, Q10 VQSUB.S32 Q13, Q15, Q14 - VQSHL.S32 Q13, Q13, #2 - VSHR.S32 Q13, Q13, #16 - VUZP.16 D26, D27 VMULL.U16 Q12, D1, D3 @@ -104,16 +99,12 @@ ixheaacd_over_lap_add1_armv7: VQMOVN.S64 D17, Q0 VREV64.32 Q3, Q3 - VQADD.S32 Q8, Q8, Q10 VQNEG.S32 Q0, Q3 VUZP.16 D1, D0 VQSUB.S32 Q9, Q12, Q8 VUZP.16 D7, D6 - VQSHL.S32 Q9, Q9, #2 VLD2.16 {D2, D3}, [R8], R12 - VSHR.S32 Q9, Q9, #16 VREV64.16 Q1, Q1 - VUZP.16 D18, D19 VLD1.32 {D4, D5}, [R1]! SUB R5, R5, #8 @@ -121,25 +112,25 @@ ixheaacd_over_lap_add1_armv7: LOOP_1: - VST1.16 D26[0], [R11], R4 + + VST1.32 D26[0], [R11], R4 VMULL.U16 Q15, D7, D2 - VST1.16 D26[1], [R11], R4 + VST1.32 D26[1], [R11], R4 VMULL.U16 Q12, D1, D3 - VST1.16 D26[2], [R11], R4 + VST1.32 D27[0], [R11] ,R4 VSHR.U32 Q15, Q15, #16 - VST1.16 D26[3], [R11], R4 + VST1.32 D27[1], [R11] ,R4 VSHR.U32 Q12, Q12, #16 - VST1.16 D18[0], [R6], R9 + VST1.32 D18[0], [R6], R9 VMLAL.S16 Q15, D6, D2 - VST1.16 D18[1], [R6], R9 + VST1.32 D18[1], [R6], R9 VMLAL.S16 Q12, D0, D3 - VST1.16 D18[2], [R6], R9 + VST1.32 D19[0], [R6], R9 VQSHL.S32 Q15, Q15, Q11 - VST1.16 D18[3], [R6], R9 + VST1.32 D19[1], [R6], R9 VQSHL.S32 Q12, Q12, Q11 VLD1.32 {D6, D7}, [R10], R12 - VADDL.S16 Q7, D3, D12 VMULL.S32 Q8, D4, D14 @@ -148,8 +139,6 @@ LOOP_1: VQMOVN.S64 D29, Q8 VREV64.32 Q3, Q3 - - VADDL.S16 Q7, D2, D12 VMULL.S32 Q0, D4, D14 @@ -160,34 +149,27 @@ LOOP_1: VLD2.16 {D2, D3}, [R8], R12 VQNEG.S32 Q0, Q3 VLD1.32 {D4, D5}, [R1]! - VQADD.S32 Q14, Q14, Q10 VUZP.16 D1, D0 - VQADD.S32 Q8, Q8, Q10 VUZP.16 D7, D6 VQSUB.S32 Q13, Q15, Q14 VREV64.16 Q1, Q1 VQSUB.S32 Q9, Q12, Q8 - VQSHL.S32 Q13, Q13, #2 - VQSHL.S32 Q9, Q9, #2 VMULL.U16 Q15, D7, D2 - VSHR.S32 Q13, Q13, #16 - VUZP.16 D26, D27 - VSHR.S32 Q9, Q9, #16 - VST1.16 D26[0], [R11], R4 + VST1.32 D26[0], [R11], R4 VMULL.U16 Q12, D1, D3 - VUZP.16 D18, D19 + VSHR.U32 Q15, Q15, #16 - VST1.16 D26[1], [R11], R4 + VST1.32 {D26[1]}, [R11], R4 VMLAL.S16 Q15, D6, D2 @MLA - VST1.16 D26[2], [R11], R4 + VST1.32 {D27[0]}, [R11], R4 VSHR.U32 Q12, Q12, #16 - VST1.16 D26[3], [R11], R4 + VST1.32 {D27[1]}, [R11], R4 VMLAL.S16 Q12, D0, D3 @MLA - VST1.16 D18[0], [R6], R9 + VST1.32 {D18[0]}, [R6], R9 VQSHL.S32 Q15, Q15, Q11 - VST1.16 D18[1], [R6], R9 + VST1.32 {D18[1]}, [R6], R9 VQSHL.S32 Q12, Q12, Q11 - VST1.16 D18[2], [R6], R9 + VST1.32 {D19[0]}, [R6], R9 VADDL.S16 Q7, D3, D12 @@ -197,7 +179,7 @@ LOOP_1: VMULL.S32 Q8, D5, D15 VQMOVN.S64 D29, Q8 - VST1.16 D18[3], [R6], R9 + VST1.32 {D19[1]}, [R6], R9 VADDL.S16 Q7, D2, D12 @@ -208,45 +190,40 @@ LOOP_1: VQMOVN.S64 D17, Q0 VLD1.32 {D6, D7}, [R10], R12 - VQADD.S32 Q14, Q14, Q10 VREV64.32 Q3, Q3 VQNEG.S32 Q0, Q3 VUZP.16 D1, D0 VQSUB.S32 Q13, Q15, Q14 VUZP.16 D7, D6 - VQADD.S32 Q8, Q8, Q10 VLD2.16 {D2, D3}, [R8], R12 VQSUB.S32 Q9, Q12, Q8 VREV64.16 Q1, Q1 - VQSHL.S32 Q13, Q13, #2 + VLD1.32 {D4, D5}, [R1]! - VQSHL.S32 Q9, Q9, #2 - VSHR.S32 Q13, Q13, #16 + SUBS R5, R5, #8 - VSHR.S32 Q9, Q9, #16 - VUZP.16 D26, D27 - VUZP.16 D18, D19 + BGT LOOP_1 - VST1.16 D26[0], [R11], R4 + VST1.32 {D26[0]}, [R11], R4 VMULL.U16 Q15, D7, D2 - VST1.16 D26[1], [R11], R4 + VST1.32 {D26[1]}, [R11], R4 VMULL.U16 Q12, D1, D3 - VST1.16 D26[2], [R11], R4 + VST1.32 {D27[0]}, [R11], R4 VSHR.U32 Q15, Q15, #16 - VST1.16 D26[3], [R11], R4 + VST1.32 {D27[1]}, [R11], R4 VSHR.U32 Q12, Q12, #16 - VST1.16 D18[0], [R6], R9 + VST1.32 {D18[0]}, [R6], R9 VMLAL.S16 Q15, D6, D2 - VST1.16 D18[1], [R6], R9 + VST1.32 {D18[1]}, [R6], R9 VMLAL.S16 Q12, D0, D3 - VST1.16 D18[2], [R6], R9 + VST1.32 {D19[0]}, [R6], R9 VQSHL.S32 Q15, Q15, Q11 - VST1.16 D18[3], [R6], R9 + VST1.32 {D19[1]}, [R6], R9 VQSHL.S32 Q12, Q12, Q11 @@ -268,29 +245,19 @@ LOOP_1: VMULL.S32 Q13, D5, D15 VQMOVN.S64 D17, Q13 - VQADD.S32 Q14, Q14, Q10 - VQADD.S32 Q8, Q8, Q10 + VQSUB.S32 Q13, Q15, Q14 VQSUB.S32 Q9, Q12, Q8 - VQSHL.S32 Q13, Q13, #2 - VQSHL.S32 Q9, Q9, #2 - VSHR.S32 Q13, Q13, #16 - VSHR.S32 Q9, Q9, #16 - VUZP.16 D26, D27 - VUZP.16 D18, D19 + VST1.32 D26[0], [R11], R4 + VST1.32 D26[1], [R11], R4 + VST1.32 D27[0], [R11], R4 + VST1.32 D27[1], [R11], R4 - - - VST1.16 D26[0], [R11], R4 - VST1.16 D26[1], [R11], R4 - VST1.16 D26[2], [R11], R4 - VST1.16 D26[3], [R11], R4 - - VST1.16 D18[0], [R6], R9 - VST1.16 D18[1], [R6], R9 - VST1.16 D18[2], [R6], R9 - VST1.16 D18[3], [R6], R9 + VST1.32 D18[0], [R6], R9 + VST1.32 D18[1], [R6], R9 + VST1.32 D19[0], [R6], R9 + VST1.32 D19[1], [R6], R9 VPOP {d8 - d15} LDMFD sp!, {R4-R12, R15} diff --git a/decoder/armv7/ixheaacd_post_twiddle_overlap.s b/decoder/armv7/ixheaacd_post_twiddle_overlap.s index 24a5ba3..57d20cd 100644 --- a/decoder/armv7/ixheaacd_post_twiddle_overlap.s +++ b/decoder/armv7/ixheaacd_post_twiddle_overlap.s @@ -44,7 +44,7 @@ ixheaacd_post_twid_overlap_add_armv7: VMOV.S16 D18, #50 RSB R9, R5, #15 - VMOV.S32 Q10, #0x00008000 + VMOV.S32 Q10, #0x0000000 VDUP.32 Q8, R5 SUB R5, R5, #16 STR R5, [sp, #116] @@ -149,14 +149,12 @@ NEXT1: VQSUB.S32 D8, D0, D8 - VQSHL.S32 D8, D8, #2 VDUP.32 D0, R8 - VQADD.S32 D8, D8, D0 - VSHR.S32 D8, D8, #16 LDR R7, [sp, #112] + LSL R7 , R7 , #1 LSL R10, R7, #1 ASR R5, R3, #1 @@ -166,8 +164,8 @@ NEXT1: MVN R9, R10 ADD R9, R9, #1 - VST1.16 D8[2], [R0], R9 - VST1.16 D8[0], [R5], R10 + VST1.32 D8[1], [R0], R9 + VST1.32 D8[0], [R5], R10 MOV R8, R1 @@ -397,28 +395,19 @@ PROLOGUE_NEON: VMLAL.S16 Q15, D15, D10 VLD2.32 {Q5, Q6}, [R6], R12 - VQSHL.S32 Q2, Q2, #2 VUZP.16 D10, D11 - VQSHL.S32 Q3, Q3, #2 VUZP.16 D12, D13 - VQADD.S32 Q7, Q2, Q10 + VMOV Q7,Q2 VREV64.16 Q5, Q5 - VQADD.S32 Q3, Q3, Q10 VREV64.16 Q6, Q6 - VSHR.S32 Q7, Q7, #16 - - VUZP.16 D14, D15 - VSHR.S32 Q3, Q3, #16 - - VUZP.16 D6, D7 - - VMOV D15, D6 VQSHL.S32 Q4, Q4, Q8 + VMOV Q9,Q3 + VLD2.32 {Q2, Q3}, [R8]! VQSHL.S32 Q15, Q15, Q8 @@ -428,72 +417,61 @@ PROLOGUE_NEON: VUZP.16 D6, D7 VQSUB.S32 Q11, Q15, Q11 - VQSHL.S32 Q15, Q4, #2 + VMOV Q15,Q4 VLD2.16 {D8, D9}, [R2]! - VQSHL.S32 Q11, Q11, #2 - - VQADD.S32 Q15, Q15, Q10 - VQADD.S32 Q11, Q11, Q10 - - VSHR.S32 Q15, Q15, #16 - - VUZP.16 D30, D31 - VSHR.S32 Q11, Q11, #16 - - - VUZP.16 D22, D23 - VMOV D23, D30 CORE_LOOP_PTO: - VST1.16 D14[0], [R0, : 16], R9 + + VST1.32 D14[0], [R0, :32], R9 + + VST1.32 D22[0], [R0, :32], R9 + + VST1.32 D14[1], [R0, :32], R9 + + VST1.32 D22[1], [R0, :32], R9 + + VST1.32 D15[0], [R0, :32], R9 + + VST1.32 D23[0], [R0, :32], R9 + + VST1.32 D15[1], [R0, :32], R9 + + VST1.32 D23[1], [R0, :32], R9 + + VST1.32 D18[0], [R5, :32], R10 + + VST1.32 D30[0], [R5, :32] ,R10 + + VST1.32 D18[1], [R5, :32], R10 + + VST1.32 D30[1], [R5, :32], R10 + + VST1.32 D19[0], [R5, :32], R10 + + VST1.32 D31[0], [R5, :32], R10 + + VST1.32 D19[1], [R5, :32], R10 + + VST1.32 D31[1], [R5, :32], R10 + VMULL.U16 Q15, D0, D9 - - VST1.16 D22[0], [R0, : 16], R9 VMULL.U16 Q14, D2, D8 - - VST1.16 D14[1], [R0, : 16], R9 VMULL.U16 Q13, D0, D8 - - VST1.16 D22[1], [R0, : 16], R9 VMULL.U16 Q12, D2, D9 - - VST1.16 D14[2], [R0, : 16], R9 VSHR.U32 Q15, Q15, #16 - - VST1.16 D22[2], [R0, : 16], R9 VSHR.U32 Q14, Q14, #16 - - VST1.16 D14[3], [R0, : 16], R9 VMLAL.S16 Q15, D1, D9 - - VST1.16 D22[3], [R0, : 16], R9 VMLAL.S16 Q14, D3, D8 - - VST1.16 D15[0], [R5, : 16], R10 VSHR.U32 Q13, Q13, #16 - - VST1.16 D23[0], [R5, : 16], R10 VSHR.U32 Q12, Q12, #16 - - VST1.16 D15[1], [R5, : 16], R10 VMLAL.S16 Q13, D1, D8 - - VST1.16 D23[1], [R5, : 16], R10 VMLAL.S16 Q12, D3, D9 - VST1.16 D15[2], [R5, : 16], R10 VADD.I32 Q15, Q15, Q14 - - VST1.16 D23[2], [R5, : 16], R10 VNEG.S32 Q15, Q15 - - VST1.16 D15[3], [R5, : 16], R10 - - VST1.16 D23[3], [R5, : 16], R10 VSUB.I32 Q14, Q12, Q13 - VMOV Q13, Q15 VMULL.U16 Q11, D4, D8 @@ -501,6 +479,7 @@ CORE_LOOP_PTO: VUZP.16 D24, D25 + VMOV.S16 D18, #50 VUZP.16 D26, D27 VMULL.U16 Q1, D24, D18 @@ -660,28 +639,21 @@ CORE_LOOP_PTO: VMLAL.S16 Q15, D15, D10 VLD2.32 {Q5, Q6}, [R6], R12 - VQSHL.S32 Q2, Q2, #2 VUZP.16 D10, D11 - VQSHL.S32 Q3, Q3, #2 VUZP.16 D12, D13 - VQADD.S32 Q7, Q2, Q10 + VMOV Q7 , Q2 VREV64.16 Q5, Q5 - VQADD.S32 Q3, Q3, Q10 VREV64.16 Q6, Q6 - VSHR.S32 Q7, Q7, #16 - VUZP.16 D14, D15 - VSHR.S32 Q3, Q3, #16 - VUZP.16 D6, D7 - - VMOV D15, D6 VQSHL.S32 Q4, Q4, Q8 + VMOV Q9,Q3 + VLD2.32 {Q2, Q3}, [R8]! VQSHL.S32 Q15, Q15, Q8 @@ -691,22 +663,9 @@ CORE_LOOP_PTO: VUZP.16 D6, D7 VQSUB.S32 Q11, Q15, Q11 - VQSHL.S32 Q15, Q4, #2 + VMOV Q15,Q4 VLD2.16 {D8, D9}, [R2]! - VQSHL.S32 Q11, Q11, #2 - - VQADD.S32 Q15, Q15, Q10 - VQADD.S32 Q11, Q11, Q10 - - VSHR.S32 Q15, Q15, #16 - - VUZP.16 D30, D31 - VSHR.S32 Q11, Q11, #16 - - - VUZP.16 D22, D23 - VMOV D23, D30 SUBS R3, R3, #1 BNE CORE_LOOP_PTO @@ -717,54 +676,57 @@ CORE_LOOP_PTO: EPILOGUE: - VST1.16 D14[0], [R0], R9 + VST1.32 D14[0], [R0], R9 + + VST1.32 D22[0], [R0], R9 + + VST1.32 D14[1], [R0], R9 + + VST1.32 D22[1], [R0], R9 + + VST1.32 D15[0], [R0], R9 + + VST1.32 D23[0], [R0], R9 + + VST1.32 D15[1], [R0], R9 + + VST1.32 D23[1], [R0], R9 + + VST1.32 D18[0], [R5], R10 + + VST1.32 D30[0], [R5], R10 + + VST1.32 D18[1], [R5], R10 + + VST1.32 D30[1], [R5], R10 + + VST1.32 D19[0], [R5], R10 + + VST1.32 D31[0], [R5], R10 + + VST1.32 D19[1], [R5], R10 + + VST1.32 D31[1], [R5], R10 + VMULL.U16 Q15, D0, D9 - - VST1.16 D22[0], [R0], R9 VMULL.U16 Q14, D2, D8 - - VST1.16 D14[1], [R0], R9 VMULL.U16 Q13, D0, D8 - - VST1.16 D22[1], [R0], R9 VMULL.U16 Q12, D2, D9 - - VST1.16 D14[2], [R0], R9 VSHR.U32 Q15, Q15, #16 - - VST1.16 D22[2], [R0], R9 VSHR.U32 Q14, Q14, #16 - - VST1.16 D14[3], [R0], R9 VMLAL.S16 Q15, D1, D9 - - VST1.16 D22[3], [R0], R9 VMLAL.S16 Q14, D3, D8 - - VST1.16 D15[0], [R5], R10 VSHR.U32 Q13, Q13, #16 - - VST1.16 D23[0], [R5], R10 VSHR.U32 Q12, Q12, #16 - - VST1.16 D15[1], [R5], R10 VMLAL.S16 Q13, D1, D8 - - VST1.16 D23[1], [R5], R10 - VMLAL.S16 Q12, D3, D9 - - VST1.16 D15[2], [R5], R10 + VMLAL.S16 Q12, D3, D9 VADD.I32 Q15, Q15, Q14 - - VST1.16 D23[2], [R5], R10 - VNEG.S32 Q15, Q15 - - VST1.16 D15[3], [R5], R10 + VNEG.S32 Q15, Q15 - VST1.16 D23[3], [R5], R10 VSUB.I32 Q14, Q12, Q13 + VMOV.S16 D18, #50 VMULL.U16 Q11, D4, D8 VMOV Q13, Q15 @@ -925,22 +887,10 @@ EPILOGUE: VMLAL.S16 Q15, D15, D10 - VQSHL.S32 Q2, Q2, #2 - VQSHL.S32 Q3, Q3, #2 VQADD.S32 Q7, Q2, Q10 - VQADD.S32 Q3, Q3, Q10 - - VSHR.S32 Q7, Q7, #16 - - VUZP.16 D14, D15 - VSHR.S32 Q3, Q3, #16 - - VUZP.16 D6, D7 - - VMOV D15, D6 VQSHL.S32 Q4, Q4, Q8 VQSHL.S32 Q15, Q15, Q8 @@ -949,40 +899,24 @@ EPILOGUE: VQSUB.S32 Q11, Q15, Q11 - VQSHL.S32 Q15, Q4, #2 + VMOV Q15 , Q4 - VQSHL.S32 Q11, Q11, #2 - - VQADD.S32 Q15, Q15, Q10 - VQADD.S32 Q11, Q11, Q10 - - VSHR.S32 Q15, Q15, #16 - - VUZP.16 D30, D31 - VSHR.S32 Q11, Q11, #16 - - VUZP.16 D22, D23 - VMOV D23, D30 - - - - - VST1.16 D14[0], [R0], R9 - VST1.16 D22[0], [R0], R9 - VST1.16 D14[1], [R0], R9 - VST1.16 D22[1], [R0], R9 - VST1.16 D14[2], [R0], R9 - VST1.16 D22[2], [R0], R9 - VST1.16 D14[3], [R0], R9 - VST1.16 D22[3], [R0], R9 - VST1.16 D15[0], [R5], R10 - VST1.16 D23[0], [R5], R10 - VST1.16 D15[1], [R5], R10 - VST1.16 D23[1], [R5], R10 - VST1.16 D15[2], [R5], R10 - VST1.16 D23[2], [R5], R10 - VST1.16 D15[3], [R5], R10 - VST1.16 D23[3], [R5], R10 + VST1.32 D14[0], [R0], R9 + VST1.32 D22[0], [R0], R9 + VST1.32 D14[1], [R0], R9 + VST1.32 D22[1], [R0], R9 + VST1.32 D15[0], [R0], R9 + VST1.32 D23[0], [R0], R9 + VST1.32 D15[1], [R0], R9 + VST1.32 D23[1], [R0], R9 + VST1.32 D6[0], [R5], R10 + VST1.32 D30[0], [R5], R10 + VST1.32 D6[1], [R5], R10 + VST1.32 D30[1], [R5], R10 + VST1.32 D7[0], [R5], R10 + VST1.32 D31[0], [R5], R10 + VST1.32 D7[1], [R5], R10 + VST1.32 D31[1], [R5], R10 ARM_EPILOGUE: @@ -1212,22 +1146,10 @@ ARM_LOOP: VMLAL.S16 Q15, D15, D10 - VQSHL.S32 Q2, Q2, #2 - VQSHL.S32 Q3, Q3, #2 - VQADD.S32 Q7, Q2, Q10 + VMOV Q7 , Q2 - VQADD.S32 Q3, Q3, Q10 - - VSHR.S32 Q7, Q7, #16 - - VUZP.16 D14, D15 - VSHR.S32 Q3, Q3, #16 - - VUZP.16 D6, D7 - - VMOV D15, D6 VQSHL.S32 Q4, Q4, Q8 VQSHL.S32 Q15, Q15, Q8 @@ -1236,39 +1158,26 @@ ARM_LOOP: VQSUB.S32 Q11, Q15, Q11 - VQSHL.S32 Q15, Q4, #2 - - VQSHL.S32 Q11, Q11, #2 - - VQADD.S32 Q15, Q15, Q10 - VQADD.S32 Q11, Q11, Q10 - - VSHR.S32 Q15, Q15, #16 - - VUZP.16 D30, D31 - VSHR.S32 Q11, Q11, #16 - - VUZP.16 D22, D23 - VMOV D23, D30 + VMOV Q15, Q4 - VST1.16 D14[0], [R0], R9 - VST1.16 D22[0], [R0], R9 - VST1.16 D14[1], [R0], R9 - VST1.16 D22[1], [R0], R9 - VST1.16 D14[2], [R0], R9 - VST1.16 D22[2], [R0], R9 - VST1.16 D14[3], [R0], R9 + VST1.32 D14[0], [R0], R9 + VST1.32 D22[0], [R0], R9 + VST1.32 D14[1], [R0], R9 + VST1.32 D22[1], [R0], R9 + VST1.32 D15[0], [R0], R9 + VST1.32 D23[0], [R0], R9 + VST1.32 D15[1], [R0], R9 - VST1.16 D15[0], [R5], R10 - VST1.16 D23[0], [R5], R10 - VST1.16 D15[1], [R5], R10 - VST1.16 D23[1], [R5], R10 - VST1.16 D15[2], [R5], R10 - VST1.16 D23[2], [R5], R10 - VST1.16 D15[3], [R5], R10 + VST1.32 D6[0], [R5], R10 + VST1.32 D30[0], [R5], R10 + VST1.32 D6[1], [R5], R10 + VST1.32 D30[1], [R5], R10 + VST1.32 D7[0], [R5], R10 + VST1.32 D31[0], [R5], R10 + VST1.32 D7[1], [R5], R10 VPOP {d8 - d15} LDMFD sp!, {R4-R12} diff --git a/decoder/armv8/ixheaacd_function_selector_armv8.c b/decoder/armv8/ixheaacd_function_selector_armv8.c index 351e472..db9c13a 100644 --- a/decoder/armv8/ixheaacd_function_selector_armv8.c +++ b/decoder/armv8/ixheaacd_function_selector_armv8.c @@ -74,7 +74,7 @@ VOID(*ixheaacd_covariance_matrix_calc_2) WORD16) = &ixheaacd_covariance_matrix_calc_2_dec; VOID(*ixheaacd_over_lap_add1) -(WORD32 *, WORD32 *, WORD16 *, const WORD16 *, WORD16, WORD16, +(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16) = &ixheaacd_over_lap_add1_armv8; VOID(*ixheaacd_over_lap_add2) @@ -159,13 +159,13 @@ VOID(*ixheaacd_post_twiddle) WORD npoints) = &ixheaacd_post_twiddle_armv8; VOID(*ixheaacd_post_twid_overlap_add) -(WORD16 pcm_out[], WORD32 spec_data[], +(WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) = &ixheaacd_post_twid_overlap_add_armv8; VOID(*ixheaacd_neg_shift_spec) -(WORD32 *coef, WORD16 *out, WORD16 q_shift, +(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) = &ixheaacd_neg_shift_spec_armv8; VOID(*ixheaacd_spec_to_overlapbuf) @@ -173,11 +173,11 @@ VOID(*ixheaacd_spec_to_overlapbuf) WORD32 size) = &ixheaacd_spec_to_overlapbuf_dec; VOID(*ixheaacd_overlap_buf_out) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) = &ixheaacd_overlap_buf_out_dec; VOID(*ixheaacd_overlap_out_copy) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac) = &ixheaacd_overlap_out_copy_dec; VOID(*ixheaacd_pretwiddle_compute) diff --git a/decoder/armv8/ixheaacd_no_lap1.s b/decoder/armv8/ixheaacd_no_lap1.s index d339879..1c71f42 100644 --- a/decoder/armv8/ixheaacd_no_lap1.s +++ b/decoder/armv8/ixheaacd_no_lap1.s @@ -53,71 +53,60 @@ ixheaacd_neg_shift_spec_armv8: ADD X6, X6, X0 MOV X8, #-16 SUB X6, X6, #12 - LSL X7, X3, #1 + LSL X7, X3, #2 DUP V31.4S, W2 - MOV W4, #0x8000 - DUP V30.4S, W4 + LD1 {V0.4S}, [X6], X8 SQNEG V0.4S, V0.4S LD1 {V6.4S}, [X6], X8 SQSHL V25.4S, V0.4S, V31.4S - SQADD V24.4S, V25.4S, V30.4S - SSHR V23.4S, V24.4S, #16 - REV64 V23.4S, V23.4S + + REV64 V25.4S, V25.4S SUB X5, X5, #8 - UZP1 V27.8H, V23.8H, V23.8H SQNEG V29.4S, V6.4S LOOP_1: - ST1 {V27.H}[2], [X1], X7 + ST1 {V25.S}[2], [X1], X7 SQSHL V22.4S, V29.4S, V31.4S LD1 {V0.4S}, [X6], X8 - ST1 {V27.H}[3], [X1], X7 - SQADD V21.4S, V22.4S, V30.4S - ST1 {V27.H}[0], [X1], X7 + ST1 {V25.S}[3], [X1], X7 + ST1 {V25.S}[0], [X1], X7 SQNEG V0.4S, V0.4S - ST1 {V27.H}[1], [X1], X7 - SSHR V20.4S, V21.4S, #16 - REV64 V20.4S, V20.4S + ST1 {V25.S}[1], [X1], X7 + REV64 V22.4S, V22.4S SUBS X5, X5, #8 - UZP1 V27.8H, V20.8H, V20.8H SQSHL V25.4S, V0.4S, V31.4S - ST1 {V27.H}[2], [X1], X7 + ST1 {V22.S}[2], [X1], X7 LD1 {V6.4S}, [X6], X8 - SQADD V24.4S, V25.4S, V30.4S - ST1 {V27.H}[3], [X1], X7 - SSHR V23.4S, V24.4S, #16 - ST1 {V27.H}[0], [X1], X7 - REV64 V23.4S, V23.4S - ST1 {V27.H}[1], [X1], X7 + ST1 {V22.S}[3], [X1], X7 + ST1 {V22.S}[0], [X1], X7 + REV64 V25.4S, V25.4S + ST1 {V22.S}[1], [X1], X7 - UZP1 V27.8H, V23.8H, V23.8H SQNEG V29.4S, V6.4S BGT LOOP_1 - ST1 {V27.H}[2], [X1], X7 + ST1 {V25.S}[2], [X1], X7 SQSHL V22.4S, V29.4S, V31.4S - ST1 {V27.H}[3], [X1], X7 - ST1 {V27.H}[0], [X1], X7 - SQADD V21.4S, V22.4S, V30.4S - ST1 {V27.H}[1], [X1], X7 - SSHR V20.4S, V21.4S, #16 + ST1 {V25.S}[3], [X1], X7 + ST1 {V25.S}[0], [X1], X7 - REV64 V20.4S, V20.4S + ST1 {V25.S}[1], [X1], X7 - UZP1 V27.8H, V20.8H, V20.8H + REV64 V22.4S, V22.4S - ST1 {V27.H}[2], [X1], X7 - ST1 {V27.H}[3], [X1], X7 - ST1 {V27.H}[0], [X1], X7 - ST1 {V27.H}[1], [X1], X7 + + ST1 {V22.S}[2], [X1], X7 + ST1 {V22.S}[3], [X1], X7 + ST1 {V22.S}[0], [X1], X7 + ST1 {V22.S}[1], [X1], X7 pop_v_regs RET diff --git a/decoder/armv8/ixheaacd_overlap_add1.s b/decoder/armv8/ixheaacd_overlap_add1.s index 14f5402..844effc 100644 --- a/decoder/armv8/ixheaacd_overlap_add1.s +++ b/decoder/armv8/ixheaacd_overlap_add1.s @@ -47,6 +47,7 @@ .global ixheaacd_over_lap_add1_armv8 ixheaacd_over_lap_add1_armv8: push_v_regs + LSL X6 , X6 , #1 LSL X10, X5, #1 SUB X11, X10, #1 LSL X10, X11, #2 @@ -58,11 +59,9 @@ ixheaacd_over_lap_add1_armv8: MOV X12, #-16 DUP V11.8H, W4 LD1 {V3.4S}, [X10], X12 - MOV W7, #0x2000 NEG W7, W7 SQNEG V0.4S, V3.4S - DUP V10.4S, W7 UZP1 V31.8H, V0.8H, V0.8H UZP2 V30.8H, V0.8H, V0.8H REV64 V31.8h, V31.8h @@ -105,12 +104,7 @@ ixheaacd_over_lap_add1_armv8: SQXTN2 V28.4S, V29.2D MOV V14.16B, V28.16B - SQADD V14.4S, V14.4S, V10.4S SQSUB V13.4S, V15.4S, V14.4S - SQSHL V13.4S, V13.4S, #2 - SSHR V13.4S, V13.4S, #16 - UZP1 V26.8H, V13.8H, V13.8H - UMULL V12.4S, V31.4H, V3.4H USHR V12.4S, V12.4S, #16 SMLAL V12.4S, V30.4H, V3.4H @@ -124,8 +118,6 @@ ixheaacd_over_lap_add1_armv8: SQXTN2 V28.4S, V29.2D MOV V8.16B, V28.16B - SQADD V8.4S, V8.4S, V10.4S - SQNEG V0.4S, V3.4S UZP1 V1.8H, V0.8H, V0.8H UZP2 V0.8H, V0.8H, V0.8H @@ -136,12 +128,9 @@ ixheaacd_over_lap_add1_armv8: UZP2 V6.8H, V3.8H, V3.8H REV64 V7.8h, V7.8h REV64 V6.8h, V6.8h - SQSHL V9.4S, V9.4S, #2 LD2 {V2.4H, V3.4H}, [X8], X12 - SSHR V9.4S, V9.4S, #16 REV64 V2.4H, V2.4H REV64 V3.4H, V3.4H - UZP1 V18.8H, V9.8H, V9.8H LD1 {V4.4S}, [X1], #16 SUB W5, W5, #8 @@ -149,21 +138,21 @@ ixheaacd_over_lap_add1_armv8: LOOP_1: - ST1 {V26.H}[0], [X11], X4 + ST1 {V13.S}[0], [X11], X4 UMULL V15.4S, V7.4H, V2.4H - ST1 {V26.H}[1], [X11], X4 + ST1 {V13.S}[1], [X11], X4 UMULL V12.4S, V1.4H, V3.4H - ST1 {V26.H}[2], [X11], X4 + ST1 {V13.S}[2], [X11], X4 USHR V15.4S, V15.4S, #16 - ST1 {V26.H}[3], [X11], X4 + ST1 {V13.S}[3], [X11], X4 USHR V12.4S, V12.4S, #16 - ST1 {V18.H}[0], [X6], X9 + ST1 {V9.S}[0], [X6], X9 SMLAL V15.4S, V6.4H, V2.4H - ST1 {V18.H}[1], [X6], X9 + ST1 {V9.S}[1], [X6], X9 SMLAL V12.4S, V0.4H, V3.4H - ST1 {V18.H}[2], [X6], X9 + ST1 {V9.S}[2], [X6], X9 SQSHL V15.4S, V15.4S, V11.4S - ST1 {V18.H}[3], [X6], X9 + ST1 {V9.S}[3], [X6], X9 SQSHL V12.4S, V12.4S, V11.4S LD1 {V6.4S}, [X10], X12 @@ -187,12 +176,10 @@ LOOP_1: LD1 {V4.4S}, [X1], #16 - SQADD V14.4S, V14.4S, V10.4S UZP1 V1.8H, V0.8H, V0.8H UZP2 V0.8H, V0.8H, V0.8H REV64 V1.8h, V1.8h REV64 V0.8h, V0.8h - SQADD V8.4S, V8.4S, V10.4S UZP1 V7.8H, V6.8H, V6.8H UZP2 V6.8H, V6.8H, V6.8H REV64 V7.8h, V7.8h @@ -201,27 +188,21 @@ LOOP_1: REV64 V2.4H, V2.4H REV64 V3.4H, V3.4H SQSUB V9.4S, V12.4S, V8.4S - SQSHL V13.4S, V13.4S, #2 - SQSHL V9.4S, V9.4S, #2 UMULL V15.4S, V7.4H, V2.4H - SSHR V13.4S, V13.4S, #16 - UZP1 V26.8H, V13.8H, V13.8H - SSHR V9.4S, V9.4S, #16 - ST1 {V26.H}[0], [X11], X4 + ST1 {V13.S}[0], [X11], X4 UMULL V12.4S, V1.4H, V3.4H - UZP1 V18.8H, V9.8H, V9.8H USHR V15.4S, V15.4S, #16 - ST1 {V26.H}[1], [X11], X4 + ST1 {V13.S}[1], [X11], X4 SMLAL V15.4S, V6.4H, V2.4H - ST1 {V26.H}[2], [X11], X4 + ST1 {V13.S}[2], [X11], X4 USHR V12.4S, V12.4S, #16 - ST1 {V26.H}[3], [X11], X4 + ST1 {V13.S}[3], [X11], X4 SMLAL V12.4S, V0.4H, V3.4H - ST1 {V18.H}[0], [X6], X9 + ST1 {V9.S}[0], [X6], X9 SQSHL V15.4S, V15.4S, V11.4S - ST1 {V18.H}[1], [X6], X9 + ST1 {V9.S}[1], [X6], X9 SQSHL V12.4S, V12.4S, V11.4S - ST1 {V18.H}[2], [X6], X9 + ST1 {V9.S}[2], [X6], X9 SSHLL V27.4S, V3.4H, #0 SMULL V28.2D, V27.2S, V4.2S @@ -230,7 +211,7 @@ LOOP_1: SQXTN2 V28.4S, V29.2D MOV V14.16B, V28.16B - ST1 {V18.H}[3], [X6], X9 + ST1 {V9.S}[3], [X6], X9 SSHLL V27.4S, V2.4H, #0 @@ -241,7 +222,6 @@ LOOP_1: MOV V8.16B, V28.16B LD1 {V3.4S}, [X10], X12 - SQADD V14.4S, V14.4S, V10.4S SQNEG V0.4S, V3.4S UZP1 V1.8H, V0.8H, V0.8H @@ -253,39 +233,35 @@ LOOP_1: UZP2 V6.8H, V3.8H, V3.8H REV64 V7.8H, V7.8H REV64 V6.8H, V6.8H - SQADD V8.4S, V8.4S, V10.4S + LD2 {V2.4H, V3.4H}, [X8], X12 SQSUB V9.4S, V12.4S, V8.4S REV64 V2.4H, V2.4H REV64 V3.4H, V3.4H - SQSHL V13.4S, V13.4S, #2 + LD1 {V4.4S}, [X1], #16 - SQSHL V9.4S, V9.4S, #2 - SSHR V13.4S, V13.4S, #16 + SUBS X5, X5, #8 - SSHR V9.4S, V9.4S, #16 - UZP1 V26.8H, V13.8H, V13.8H - UZP1 V18.8H, V9.8H, V9.8H BGT LOOP_1 - ST1 {V26.H}[0], [X11], X4 + ST1 {V13.S}[0], [X11], X4 UMULL V15.4S, V7.4H, V2.4H - ST1 {V26.H}[1], [X11], X4 + ST1 {V13.S}[1], [X11], X4 UMULL V12.4s, V1.4H, V3.4H - ST1 {V26.H}[2], [X11], X4 + ST1 {V13.S}[2], [X11], X4 USHR V15.4S, V15.4S, #16 - ST1 {V26.H}[3], [X11], X4 + ST1 {V13.S}[3], [X11], X4 USHR V12.4S, V12.4S, #16 - ST1 {V18.H}[0], [X6], X9 + ST1 {V9.S}[0], [X6], X9 SMLAL V15.4S, V6.4H, V2.4H - ST1 {V18.H}[1], [X6], X9 + ST1 {V9.S}[1], [X6], X9 SMLAL V12.4S, V0.4H, V3.4H - ST1 {V18.H}[2], [X6], X9 + ST1 {V9.S}[2], [X6], X9 SQSHL V15.4S, V15.4S, V11.4S - ST1 {V18.H}[3], [X6], X9 + ST1 {V9.S}[3], [X6], X9 SQSHL V12.4S, V12.4S, V11.4S @@ -303,28 +279,20 @@ LOOP_1: SQXTN2 V28.4S, V29.2D MOV V8.16B, V28.16B - SQADD V14.4S, V14.4S, V10.4S - SQADD V8.4S, V8.4S, V10.4S + SQSUB V13.4S, V15.4S, V14.4S SQSUB V9.4S, V12.4S, V8.4S - SQSHL V13.4S, V13.4S, #2 - SQSHL V9.4S, V9.4S, #2 - SSHR V13.4S, V13.4S, #16 - SSHR V9.4S, V9.4S, #16 - UZP1 V26.8H, V13.8H, V13.8H - - UZP1 V18.8H, V9.8H, V9.8H - ST1 {V26.H}[0], [X11], X4 - ST1 {V26.H}[1], [X11], X4 - ST1 {V26.H}[2], [X11], X4 - ST1 {V26.H}[3], [X11], X4 + ST1 {V13.S}[0], [X11], X4 + ST1 {V13.S}[1], [X11], X4 + ST1 {V13.S}[2], [X11], X4 + ST1 {V13.S}[3], [X11], X4 - ST1 {V18.H}[0], [X6], X9 - ST1 {V18.H}[1], [X6], X9 - ST1 {V18.H}[2], [X6], X9 - ST1 {V18.H}[3], [X6], X9 + ST1 {V9.S}[0], [X6], X9 + ST1 {V9.S}[1], [X6], X9 + ST1 {V9.S}[2], [X6], X9 + ST1 {V9.S}[3], [X6], X9 pop_v_regs RET diff --git a/decoder/armv8/ixheaacd_post_twiddle_overlap.s b/decoder/armv8/ixheaacd_post_twiddle_overlap.s index b8ee331..f05e6e4 100644 --- a/decoder/armv8/ixheaacd_post_twiddle_overlap.s +++ b/decoder/armv8/ixheaacd_post_twiddle_overlap.s @@ -1,43 +1,43 @@ .macro push_v_regs - stp q8, q9, [sp, #-32]! - stp q10, q11, [sp, #-32]! - stp q12, q13, [sp, #-32]! - stp q14, q15, [sp, #-32]! + stp q8, q9, [sp, #-32]! + stp q10, q11, [sp, #-32]! + stp q12, q13, [sp, #-32]! + stp q14, q15, [sp, #-32]! //st1 { v8.2d, v9.2d, v10.2d, v11.2d}, [sp, #-64]! //st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp, #-64]! - stp X8, X9, [sp, #-16]! - stp X10, X11, [sp, #-16]! - stp X12, X13, [sp, #-16]! - stp X14, X15, [sp, #-16]! - stp X16, X17, [sp, #-16]! - stp X18, X19, [sp, #-16]! - stp X20, X21, [sp, #-16]! - stp X22, X23, [sp, #-16]! - stp X24, X25, [sp, #-16]! - stp X26, X27, [sp, #-16]! - stp X28, X29, [sp, #-16]! - stp X30, X29, [sp, #-16]! + stp X8, X9, [sp, #-16]! + stp X10, X11, [sp, #-16]! + stp X12, X13, [sp, #-16]! + stp X14, X15, [sp, #-16]! + stp X16, X17, [sp, #-16]! + stp X18, X19, [sp, #-16]! + stp X20, X21, [sp, #-16]! + stp X22, X23, [sp, #-16]! + stp X24, X25, [sp, #-16]! + stp X26, X27, [sp, #-16]! + stp X28, X29, [sp, #-16]! + stp X30, X29, [sp, #-16]! .endm .macro pop_v_regs - ldp X30, X29, [sp], #16 - ldp X28, X29, [sp], #16 - ldp X26, X27, [sp], #16 - ldp X24, X25, [sp], #16 - ldp X22, X23, [sp], #16 - ldp X20, X21, [sp], #16 - ldp X18, X19, [sp], #16 - ldp X16, X17, [sp], #16 - ldp X14, X15, [sp], #16 - ldp X12, X13, [sp], #16 - ldp X10, X11, [sp], #16 - ldp X8, X9, [sp], #16 + ldp X30, X29, [sp], #16 + ldp X28, X29, [sp], #16 + ldp X26, X27, [sp], #16 + ldp X24, X25, [sp], #16 + ldp X22, X23, [sp], #16 + ldp X20, X21, [sp], #16 + ldp X18, X19, [sp], #16 + ldp X16, X17, [sp], #16 + ldp X14, X15, [sp], #16 + ldp X12, X13, [sp], #16 + ldp X10, X11, [sp], #16 + ldp X8, X9, [sp], #16 //ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64 //ld1 { v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64 - ldp q14, q15, [sp], #32 - ldp q12, q13, [sp], #32 - ldp q10, q11, [sp], #32 - ldp q8, q9, [sp], #32 + ldp q14, q15, [sp], #32 + ldp q12, q13, [sp], #32 + ldp q10, q11, [sp], #32 + ldp q8, q9, [sp], #32 .endm @@ -48,18 +48,18 @@ ixheaacd_post_twid_overlap_add_armv8: // STMFD sp!, {x4-x12} - push_v_regs - //stp x19, x20,[sp,#-16]! + push_v_regs + //stp x19, x20,[sp,#-16]! //VPUSH {d8 - d15} //LDR w4, [sp, #100] - //sxtw x4,w4 + //sxtw x4,w4 //LDR w5, [sp, #104] - //sxtw x5,w5 + //sxtw x5,w5 //LDR w6, [sp, #108] - //sxtw x6,w6 - MOV x16, x5 - MOV x17, x7 + //sxtw x6,w6 + MOV x16, x5 + MOV x17, x7 LSL x9, x3, #2 ASR x9, x9, #1 ADD x6, x6, x9 @@ -71,141 +71,141 @@ ixheaacd_post_twid_overlap_add_armv8: - movi v18.4h, #50 - sub x20, x5, #15 - neg x9, x20 - movi v20.4s, #0x80, LSL #8 - dup v16.4s, w5 + movi v18.4h, #50 + sub x20, x5, #15 + neg x9, x20 + movi v20.4s, #0x00, LSL #8 + dup v16.4s,w5 SUB x5, x5, #16 //STR w5, [sp, #116] - MOV w25, w5 - sxtw x25, w25 + MOV w25, w5 + sxtw x25,w25 MOV x8, #1 LSL x8, x8, x9 //STR w8, [sp, #120] - MOV w26, w8 + MOV w26, w8 - //sxtw x8,w8 + //sxtw x8,w8 ARM_PROLOGUE: - LDR w8, [x1], #4 - sxtw x8, w8 - LDR w9, [x1], #4 - sxtw x9, w9 + LDR w8, [x1], #4 + sxtw x8,w8 + LDR w9, [x1], #4 + sxtw x9,w9 - LDR w10, [x2], #4 - sxtw x10, w10 + LDR w10, [x2], #4 + sxtw x10,w10 - AND w19, w10, 0xFFFF - sxth x19, w19 - ASR w10, w10, #16 + AND w19,w10,0xFFFF + sxth x19,w19 + ASR w10,w10,#16 // SMULWT x11, x8, x10 // -// SMULWB x12, x9, x10 +// SMULWB x12, x9, x10 // SMULWB x5, x8, x10 // SMLAWT x7, x9, x10, x5 - SMULL x11, w8, w10 - ASR x11, x11, #16 - SMULL x12, w9, w19 - ASR x12, x12, #16 - SMULL x5, w8, w19 - ASR x5, x5, #16 - SMULL x7, w9, w10 - ASR x7, x7, #16 - ADD x7, x7, x5 + SMULL x11, w8, w10 + ASR x11,x11,#16 + SMULL x12, w9, w19 + ASR x12,x12,#16 + SMULL x5, w8, w19 + ASR x5,x5,#16 + SMULL x7, w9, w10 + ASR x7, x7, #16 + ADD x7, x7, x5 - SUB x8, x12, x11 + SUB x8, x12, x11 MVN x5, x7 ADD x5, x5, #1 MOV x9, #50 MOV x12, #-50 - AND w19, w9, 0xFFFF - sxth x19, w19 - SMULL x10, w5, w19 - ASR x10, x10, #16 - AND w19, w12, 0xFFFF - sxth x19, w19 - SMULL x11, w8, w19 - ASR x11, x11, #16 + AND w19,w9,0xFFFF + sxth x19,w19 + SMULL x10, w5, w19 + ASR x10,x10,#16 + AND w19,w12,0xFFFF + sxth x19,w19 + SMULL x11, w8, w19 + ASR x11,x11,#16 - ADD x8, x8, x10 + ADD x8, x8, x10 ADD x5, x5, x11 //LDR w11, [sp, #104] - MOV w11, w16 - sxth x11, w11 - LDR w10, [x6], #-32 - sxtw x10, w10 + MOV w11, w16 + sxth x11,w11 + LDR w10, [x6], #-32 + sxtw x10,w10 - AND w19, w10, 0xFFFF - sxth x19, w19 - ASR w20, w10, #16 + AND w19,w10,0xFFFF + sxth x19,w19 + ASR w20,w10,#16 //SMULWB x7, x8, x10 - SMULL x7, w8, w19 - ASR x7, x7, #16 - MVN x8, x8 + SMULL x7, w8, w19 + ASR x7, x7, #16 + MVN x8, x8 ADD x8, x8, #1 //SMULWT x12, x8, x10 - SMULL x12, w8, w20 - ASR x12, x12, #16 + SMULL x12, w8, w20 + ASR x12, x12, #16 CMP x11, #0 BLT NEXT - SUB x9, x11, #16 - negs x9, x9 + SUB x9, x11, #16 + negs x9,x9 - // LDR w8, [sp, #120] - //sxtw x8,w8 - MOV v1.s[0], w26 - MOV v2.s[0], w5 + // LDR w8, [sp, #120] + //sxtw x8,w8 + MOV v1.s[0], w26 + MOV v2.s[0], w5 //sQADD w5, w5, w8 //ASR w5, w5, w9 - SQADD v2.2s, v2.2s, v1.2s - MOV w5, v2.s[0] - ASR w5, w5, w9 + SQADD v2.2s, v2.2s, v1.2s + MOV w5, v2.s[0] + ASR w5, w5, w9 - SUB x9, x11, #31 - negs x9, x9 - ASR x20, x7, x9 + SUB x9, x11, #31 + negs x9,x9 + ASR x20, x7, x9 //MOV x8, x20 - ADDS x8, x20, #0 - BGE NEXT2 - CMN x8, #1 + ADDS x8, x20, #0 + BGE NEXT2 + CMN x8, #1 NEXT2: MOV x20, #0x80000000 - csel x7, x20, x7, LT + csel x7, x20, x7,LT MOV x20, #0x7fffffff - csel x7, x20, x7, GT - LSL x20, x7, x11 - csel x7, x20, x7, EQ + csel x7, x20, x7,GT + LSL x20, x7, x11 + csel x7,x20,x7,EQ - SUB x9, x11, #31 - negs x9, x9 - ASR x20, x12, x9 + SUB x9, x11, #31 + negs x9,x9 + ASR x20, x12, x9 //MOV x8, x20 - ADDS x8, x20, #0 - BGE NEXT3 - CMN x8, #1 + ADDS x8, x20, #0 + BGE NEXT3 + CMN x8, #1 NEXT3: MOV x20, #0x80000000 - csel x12, x20, x12, LT + csel x12, x20, x12,LT MOV x20, #0x7fffffff - csel x12, x20, x12, GT - LSL x20, x12, x11 - csel x12, x20, x12, EQ + csel x12, x20, x12,GT + LSL x20, x12, x11 + csel x12,x20,x12,EQ B NEXT1 NEXT: @@ -214,83 +214,83 @@ NEXT: ASR w5, w5, w11 MOV w8, #0x8000 - MOV v1.s[0], w8 - MOV v2.s[0], w5 + MOV v1.s[0], w8 + MOV v2.s[0], w5 //QADD x5, x5, x8 - SQADD v2.2s, v2.2s, v1.2s - MOV w5, v2.s[0] + SQADD v2.2s, v2.2s, v1.2s + MOV w5, v2.s[0] - ASR w5, w5, #16 + ASR w5, w5, #16 ASR w7, w7, w11 ASR w12, w12, w11 NEXT1: - LDR w9, [x4] - sxtw x9, w9 + LDR w9, [x4] + sxtw x9,w9 MOV w8, #0x8000 - //sxtw x8,w8 + //sxtw x8,w8 - STR w5, [x4], #4 - sxtw x5, w5 + STR w5, [x4], #4 + sxtw x5,w5 - ROR w20, w10, #16 + ROR w20, w10, #16 //UXTH x5, x10, ROR #16 - UXTH w5, w20 - UXTH w10, w10 + UXTH w5, w20 + UXTH w10, w10 - dup v0.2s, w9 - dup v2.2s, w10 - dup v3.2s, w5 + dup v0.2s,w9 + dup v2.2s,w10 + dup v3.2s,w5 //VZIP.32 D2, D3 - ZIP1 v28.2s, v2.2s, v3.2s - ZIP2 v3.2s, v2.2s, v3.2s - MOV v2.8b, v28.8b - sMULL v0.2d, v2.2s, v0.2s - Sqxtn v8.2s, v0.2d + ZIP1 v28.2s, v2.2s, v3.2s + ZIP2 v3.2s, v2.2s, v3.2s + MOV v2.8b, v28.8b + sMULL v0.2d, v2.2s, v0.2s + Sqxtn v8.2s, v0.2d - dup v0.2s, w12 - dup v1.2s, w7 + dup v0.2s,w12 + dup v1.2s,w7 //VZIP.32 D0, D1 - ZIP1 v28.2s, v0.2s, v1.2s - ZIP2 v1.2s, v0.2s, v1.2s - MOV v0.8b, v28.8b + ZIP1 v28.2s, v0.2s, v1.2s + ZIP2 v1.2s, v0.2s, v1.2s + MOV v0.8b, v28.8b - SQSUB v8.2s, v0.2s , v8.2s + SQSUB v8.2s, v0.2s , v8.2s - sQshL v8.2s, v8.2s, #2 - dup v0.2s, w8 - SQADD v8.2s, v8.2s , v0.2s - sshR v8.2s, v8.2s, #16 + //sQshL v8.2s, v8.2s,#2 + dup v0.2s,w8 + //SQADD v8.2s, v8.2s , v0.2s + //sshR v8.2s, v8.2s,#16 - MOV x7, x17 - //sxtw x7,w7 - LSL x10, x7, #1 + MOV x7, x17 + //sxtw x7,w7 + LSL x10, x7, #2 ASR x5, x3, #1 //SMULBB x5, x10, x5 - AND w5, w5, 0xFFFF - sxth x5, w5 - AND w19, w10, 0xFFFF - sxth x19, w19 - SMULL x5, w19, w5 + AND w5,w5,0xFFFF + sxth x5,w5 + AND w19,w10,0xFFFF + sxth x19,w19 + SMULL x5, w19, w5 ADD x5, x5, x0 SUB x0, x5, x10 MVN x9, x10 ADD x9, x9, #1 - ST1 {v8.h}[2], [x0], x9 - ST1 {v8.h}[0], [x5], x10 + ST1 {V8.S}[1],[x0], x9 + ST1 {V8.S}[0],[x5], x10 MOV x8, x1 @@ -311,875 +311,799 @@ PROLOGUE_NEON: ASR x3, x3, #2 SUB x3, x3, #2 - LD2 { v0.4s, v1.4s}, [x1] - MOV v2.16b, v1.16b - ADD x1, x1, x12 + LD2 { v0.4s, v1.4s}, [x1] + MOV v2.16b, v1.16b + ADD x1, x1, x12 //VUZP.16 D0, D1 - UZP1 v28.8h, v0.8h, v0.8h - UZP2 v29.8h, v0.8h, v0.8h - MOV v0.d[0], v28.d[0] - MOV v0.d[1], v29.d[0] + UZP1 v28.8h, v0.8h, v0.8h + UZP2 v29.8h, v0.8h, v0.8h + MOV v0.d[0], v28.d[0] + MOV v0.d[1], v29.d[0] - //VUZP.16 D2, D3 + //VUZP.16 D2, D3 - UZP1 v28.8h, v2.8h, v2.8h - UZP2 v29.8h, v2.8h, v2.8h - MOV v2.d[0], v28.d[0] - MOV v2.d[1], v29.d[0] + UZP1 v28.8h, v2.8h, v2.8h + UZP2 v29.8h, v2.8h, v2.8h + MOV v2.d[0], v28.d[0] + MOV v2.d[1], v29.d[0] //rev64 v0.8h, v0.8h - rev64 v0.8h, v0.8h - MOV v1.d[0], v0.d[1] - rev64 v2.8h, v2.8h - MOV v3.d[0], v2.d[1] - LD2 {v8.4h, v9.4h}, [x2] - ADD x2, x2, #16 + rev64 v0.8h, v0.8h + MOV v1.d[0], v0.d[1] + rev64 v2.8h, v2.8h + MOV v3.d[0], v2.d[1] + LD2 {v8.4h, v9.4h}, [x2] + ADD x2, x2, #16 - LD2 { v4.4s, v5.4s}, [x8] - MOV v6.16b, v5.16b - ADD x8, x8, #32 - uMULL v30.4s, v0.4h, v9.4h + LD2 { v4.4s, v5.4s}, [x8] + MOV v6.16b, v5.16b + ADD x8, x8,#32 + uMULL v30.4s, v0.4h, v9.4h // VUZP.16 D4, D5 - UZP1 v28.8h, v4.8h, v4.8h - UZP2 v29.8h, v4.8h, v4.8h - MOV v4.d[0], v28.d[0] - MOV v5.d[0], v29.d[0] + UZP1 v28.8h, v4.8h, v4.8h + UZP2 v29.8h, v4.8h, v4.8h + MOV v4.d[0], v28.d[0] + MOV v5.d[0], v29.d[0] - uMULL v28.4s, v2.4h, v8.4h + uMULL v28.4s, v2.4h, v8.4h // VUZP.16 D6, D7 - UZP1 v26.8h, v6.8h, v6.8h - UZP2 v27.8h, v6.8h, v6.8h - MOV v6.d[0], v26.d[0] - MOV v7.d[0], v27.d[0] + UZP1 v26.8h, v6.8h, v6.8h + UZP2 v27.8h, v6.8h, v6.8h + MOV v6.d[0], v26.d[0] + MOV v7.d[0], v27.d[0] - uMULL v26.4s, v0.4h, v8.4h + uMULL v26.4s, v0.4h, v8.4h - uMULL v24.4s, v2.4h, v9.4h + uMULL v24.4s, v2.4h, v9.4h - LD2 { v10.4s, v11.4s}, [x6] - MOV v12.16b, v11.16b - ADD x6, x6, x12 - ushR v30.4s, v30.4s, #16 + LD2 { v10.4s, v11.4s}, [x6] + MOV v12.16b, v11.16b + ADD x6, x6, x12 + ushR v30.4s, v30.4s,#16 //VUZP.16 D10, D11 - UZP1 v22.8h, v10.8h, v10.8h - UZP2 v23.8h, v10.8h, v10.8h - MOV v10.d[0], v22.d[0] - MOV v10.d[1], v23.d[0] + UZP1 v22.8h, v10.8h, v10.8h + UZP2 v23.8h, v10.8h, v10.8h + MOV v10.d[0], v22.d[0] + MOV v10.d[1], v23.d[0] - ushR v28.4s, v28.4s, #16 + ushR v28.4s, v28.4s,#16 //VUZP.16 D12, D13 - UZP1 v22.8h, v12.8h, v12.8h - UZP2 v23.8h, v12.8h, v12.8h - MOV v12.d[0], v22.d[0] - MOV v12.d[1], v23.d[0] + UZP1 v22.8h, v12.8h, v12.8h + UZP2 v23.8h, v12.8h, v12.8h + MOV v12.d[0], v22.d[0] + MOV v12.d[1], v23.d[0] - sMLAL v30.4s, v1.4h, v9.4h + sMLAL v30.4s, v1.4h, v9.4h - rev64 v10.8h, v10.8h - MOV v11.d[0], v10.d[1] - sMLAL v28.4s, v3.4h, v8.4h + rev64 v10.8h, v10.8h + MOV v11.d[0], v10.d[1] + sMLAL v28.4s, v3.4h, v8.4h - rev64 v12.8h, v12.8h - MOV v13.d[0], v12.d[1] - ushR v26.4s, v26.4s, #16 + rev64 v12.8h, v12.8h + MOV v13.d[0], v12.d[1] + ushR v26.4s, v26.4s,#16 - ushR v24.4s, v24.4s, #16 + ushR v24.4s, v24.4s,#16 - sMLAL v26.4s, v1.4h, v8.4h - sMLAL v24.4s, v3.4h, v9.4h + sMLAL v26.4s, v1.4h, v8.4h + sMLAL v24.4s, v3.4h, v9.4h - ADD v30.4s, v30.4s , v28.4s - NEG v30.4s, v30.4s + ADD v30.4s, v30.4s , v28.4s + NEG v30.4s, v30.4s - uMULL v22.4s, v4.4h, v8.4h + uMULL v22.4s, v4.4h, v8.4h - SUB v28.4s, v24.4s , v26.4s + SUB v28.4s, v24.4s , v26.4s - mov v26.16b, v30.16b - mov v24.16b, v28.16b + mov v26.16b, v30.16b + mov v24.16b, v28.16b // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - uMULL v2.4s, v24.4h, v18.4h + uMULL v2.4s, v24.4h, v18.4h - uMULL v0.4s, v26.4h, v18.4h + uMULL v0.4s, v26.4h, v18.4h - ushR v22.4s, v22.4s, #16 - sMLAL v22.4s, v5.4h, v8.4h + ushR v22.4s, v22.4s,#16 + sMLAL v22.4s, v5.4h, v8.4h - ushR v2.4s, v2.4s, #16 - ushR v0.4s, v0.4s, #16 - sMLAL v2.4s, v25.4h, v18.4h - sMLAL v0.4s, v27.4h, v18.4h + ushR v2.4s, v2.4s,#16 + ushR v0.4s, v0.4s,#16 + sMLAL v2.4s, v25.4h, v18.4h + sMLAL v0.4s, v27.4h, v18.4h - uMULL v24.4s, v4.4h, v9.4h - uMULL v26.4s, v6.4h, v8.4h + uMULL v24.4s, v4.4h, v9.4h + uMULL v26.4s, v6.4h, v8.4h - NEG v2.4s, v2.4s - ADD v28.4s, v28.4s , v0.4s - ADD v30.4s, v30.4s , v2.4s + NEG v2.4s, v2.4s + ADD v28.4s, v28.4s , v0.4s + ADD v30.4s, v30.4s , v2.4s - uMULL v0.4s, v6.4h, v9.4h - sshR v24.4s, v24.4s, #16 - sMLAL v24.4s, v5.4h, v9.4h - sshR v26.4s, v26.4s, #16 - sshR v0.4s, v0.4s, #16 - sMLAL v26.4s, v7.4h, v8.4h - sMLAL v0.4s, v7.4h, v9.4h + uMULL v0.4s, v6.4h, v9.4h + sshR v24.4s, v24.4s,#16 + sMLAL v24.4s, v5.4h, v9.4h + sshR v26.4s, v26.4s,#16 + sshR v0.4s, v0.4s,#16 + sMLAL v26.4s, v7.4h, v8.4h + sMLAL v0.4s, v7.4h, v9.4h - ADD v22.4s, v22.4s , v0.4s - NEG v22.4s, v22.4s - SUB v24.4s, v26.4s , v24.4s + ADD v22.4s, v22.4s , v0.4s + NEG v22.4s, v22.4s + SUB v24.4s, v26.4s , v24.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v14.4s, w11 - SQADD v28.4s, v28.4s , v14.4s + //sxtw x11,w11 + MOV w11, w26 + dup v14.4s,w11 + SQADD v28.4s, v28.4s , v14.4s //LDR w11, [sp, #116] - MOV w11, w25 - //sxtw x11,w11 - dup v0.4s, w11 - sQshL v28.4s, v28.4s, v0.4s + MOV w11, w25 + //sxtw x11,w11 + dup v0.4s,w11 + sQshL v28.4s, v28.4s, v0.4s - mov v0.16b, v22.16b - mov v14.16b, v24.16b + mov v0.16b, v22.16b + mov v14.16b, v24.16b // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] // VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] + UZP1 v19.8h, v22.8h, v22.8h + UZP2 v21.8h, v22.8h, v22.8h + MOV v22.d[0], v19.d[0] + MOV v23.d[0], v21.d[0] - uMULL v8.4s, v24.4h, v18.4h - uMULL v26.4s, v22.4h, v18.4h + uMULL v8.4s, v24.4h, v18.4h + uMULL v26.4s, v22.4h, v18.4h - NEG v2.4s, v30.4s + NEG v2.4s, v30.4s // VUZP.16 D30, D31 - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] + UZP1 v19.8h, v30.8h, v30.8h + UZP2 v21.8h, v30.8h, v30.8h + MOV v30.d[0], v19.d[0] + MOV v30.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v3.d[0], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v3.d[0], v21.d[0] - uMULL v4.4s, v30.4h, v12.4h + uMULL v4.4s, v30.4h, v12.4h - uMULL v6.4s, v2.4h, v13.4h + uMULL v6.4s, v2.4h, v13.4h - ushR v8.4s, v8.4s, #16 - ushR v26.4s, v26.4s, #16 + ushR v8.4s, v8.4s,#16 + ushR v26.4s, v26.4s,#16 - sMLAL v8.4s, v25.4h, v18.4h - sMLAL v26.4s, v23.4h, v18.4h + sMLAL v8.4s, v25.4h, v18.4h + sMLAL v26.4s, v23.4h, v18.4h - ushR v4.4s, v4.4s, #16 - ushR v6.4s, v6.4s, #16 + ushR v4.4s, v4.4s,#16 + ushR v6.4s, v6.4s,#16 - MOV v19.d[0], v30.d[1] + MOV v19.d[0], v30.d[1] - sMLAL v4.4s, v19.4h, v12.4h - sMLAL v6.4s, v3.4h, v13.4h + sMLAL v4.4s, v19.4h, v12.4h + sMLAL v6.4s, v3.4h, v13.4h - NEG v8.4s, v8.4s - ADD v14.4s, v14.4s , v26.4s - ADD v0.4s, v0.4s , v8.4s + NEG v8.4s, v8.4s + ADD v14.4s, v14.4s , v26.4s + ADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v8.4s, w11 - SQADD v0.4s, v0.4s , v8.4s + //sxtw x11,w11 + MOV w11, w26 + dup v8.4s,w11 + SQADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v26.4s, w11 - sQshL v0.4s, v0.4s, v26.4s + //sxtw x11,w11 + MOV w11, w25 + dup v26.4s,w11 + sQshL v0.4s, v0.4s, v26.4s - mov v26.16b, v28.16b + mov v26.16b, v28.16b - LD2 { v28.4s, v29.4s}, [x4] - MOV v30.16b, v29.16b - MOV v29.d[0], v28.d[1] -// VZIP.32 Q13, Q0 + LD2 { v28.4s, v29.4s}, [x4] + MOV v30.16b, v29.16b + MOV v29.d[0], v28.d[1] + // VZIP.32 Q13, Q0 - ZIP1 v19.4s, v26.4s, v0.4s - ZIP2 v0.4s, v26.4s, v0.4s - MOV v26.16b, v19.16b + ZIP1 v19.4s, v26.4s, v0.4s + ZIP2 v0.4s, v26.4s, v0.4s + MOV v26.16b, v19.16b - ST1 { v26.4s}, [x4], #16 - ST1 { v0.4s}, [x4], #16 + ST1 { v26.4s}, [x4],#16 + ST1 { v0.4s}, [x4],#16 - movi v1.2s, #0 + movi v1.2s, #0 //VADDL.S16 Q0, D13, D1 - SADDL v0.4s, v13.4h, v1.4h - MOV v1.d[0], v0.d[1] - sMULL v26.2d, v28.2s, v0.2s - Sqxtn v8.2s, v26.2d - sMULL v26.2d, v29.2s, v1.2s - Sqxtn v9.2s, v26.2d - MOV v8.d[1], v9.d[0] - movi v1.2s, #0 + SADDL v0.4s, v13.4h, v1.4h + MOV v1.d[0], v0.d[1] + sMULL v26.2d, v28.2s, v0.2s + Sqxtn v8.2s, v26.2d + sMULL v26.2d, v29.2s, v1.2s + Sqxtn v9.2s, v26.2d + MOV v8.d[1], v9.d[0] + movi v1.2s, #0 // VADDL.S16 Q0, D12, D1 - SADDL v0.4s, v12.4h, v1.4h - MOV v1.d[0], v0.d[1] - sMULL v24.2d, v28.2s, v0.2s - Sqxtn v26.2s, v24.2d - sMULL v24.2d, v29.2s, v1.2s - Sqxtn v27.2s, v24.2d - MOV v26.d[1], v27.d[0] + SADDL v0.4s, v12.4h, v1.4h + MOV v1.d[0], v0.d[1] + sMULL v24.2d, v28.2s, v0.2s + Sqxtn v26.2s, v24.2d + sMULL v24.2d, v29.2s, v1.2s + Sqxtn v27.2s, v24.2d + MOV v26.d[1], v27.d[0] - sQshL v4.4s, v4.4s, v16.4s - sQshL v6.4s, v6.4s, v16.4s + sQshL v4.4s, v4.4s, v16.4s + sQshL v6.4s, v6.4s, v16.4s - SQSUB v4.4s, v4.4s , v8.4s - SQSUB v6.4s, v6.4s , v26.4s + SQSUB v4.4s, v4.4s , v8.4s + SQSUB v6.4s, v6.4s , v26.4s - NEG v26.4s, v14.4s + NEG v26.4s, v14.4s // VUZP.16 D14, D15 - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + UZP1 v19.8h, v14.8h, v14.8h + UZP2 v21.8h, v14.8h, v14.8h + MOV v14.d[0], v19.d[0] + MOV v15.d[0], v21.d[0] // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - movi v1.2s, #0 + movi v1.2s, #0 // VADDL.S16 Q0, D10, D1 - SADDL v0.4s, v10.4h, v1.4h - MOV v1.d[0], v0.d[0] - sMULL v22.2d, v30.2s, v0.2s - Sqxtn v24.2s, v22.2d - sMULL2 v22.2d, v30.4s, v0.4s - Sqxtn v25.2s, v22.2d - MOV v24.d[1], v25.d[0] - movi v1.2s, #0 + SADDL v0.4s, v10.4h, v1.4h + MOV v1.d[0], v0.d[0] + sMULL v22.2d, v30.2s, v0.2s + Sqxtn v24.2s, v22.2d + sMULL2 v22.2d, v30.4s, v0.4s + Sqxtn v25.2s, v22.2d + MOV v24.d[1], v25.d[0] + movi v1.2s, #0 // VADDL.S16 Q0, D11, D1 - SADDL v0.4s, v11.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v11.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v8.2d, v30.2s, v0.2s - Sqxtn v22.2s, v8.2d - sMULL2 v8.2d, v30.4s, v0.4s - Sqxtn v23.2s, v8.2d - MOV v22.d[1], v23.d[0] - uMULL v8.4s, v26.4h, v11.4h - uMULL v30.4s, v14.4h, v10.4h + sMULL v8.2d, v30.2s, v0.2s + Sqxtn v22.2s, v8.2d + sMULL2 v8.2d, v30.4s, v0.4s + Sqxtn v23.2s, v8.2d + MOV v22.d[1], v23.d[0] + uMULL v8.4s, v26.4h, v11.4h + uMULL v30.4s, v14.4h, v10.4h - LD2 { v0.4s, v1.4s}, [x1] - MOV v2.16b, v1.16b - ADD x1, x1, x12 + LD2 { v0.4s, v1.4s}, [x1] + MOV v2.16b, v1.16b + ADD x1, x1, x12 // VUZP.16 D0, D1 - UZP1 v19.8h, v0.8h, v0.8h - UZP2 v21.8h, v0.8h, v0.8h - MOV v0.d[0], v19.d[0] - MOV v0.d[1], v21.d[0] + UZP1 v19.8h, v0.8h, v0.8h + UZP2 v21.8h, v0.8h, v0.8h + MOV v0.d[0], v19.d[0] + MOV v0.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v2.d[1], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v2.d[1], v21.d[0] - ushR v8.4s, v8.4s, #16 + ushR v8.4s, v8.4s,#16 - rev64 v0.8h, v0.8h - MOV v1.d[0], v0.d[1] - ushR v30.4s, v30.4s, #16 + rev64 v0.8h, v0.8h + MOV v1.d[0], v0.d[1] + ushR v30.4s, v30.4s,#16 - rev64 v2.8h, v2.8h - MOV v3.d[0], v2.d[1] - sMLAL v8.4s, v27.4h, v11.4h + rev64 v2.8h, v2.8h + MOV v3.d[0], v2.d[1] + sMLAL v8.4s, v27.4h, v11.4h - sMLAL v30.4s, v15.4h, v10.4h + sMLAL v30.4s, v15.4h, v10.4h - LD2 { v10.4s, v11.4s}, [x6] - ADD x6, x6, x12 - MOV v12.16b, v11.16b - sQshL v4.4s, v4.4s, #2 + LD2 { v10.4s, v11.4s}, [x6] + ADD x6, x6, x12 + MOV v12.16b, v11.16b -// VUZP.16 D10, D11 + UZP1 v19.8h, v10.8h, v10.8h + UZP2 v21.8h, v10.8h, v10.8h + MOV v10.d[0], v19.d[0] + MOV v10.d[1], v21.d[0] - UZP1 v19.8h, v10.8h, v10.8h - UZP2 v21.8h, v10.8h, v10.8h - MOV v10.d[0], v19.d[0] - MOV v10.d[1], v21.d[0] - sQshL v6.4s, v6.4s, #2 + UZP1 v19.8h, v12.8h, v12.8h + UZP2 v21.8h, v12.8h, v12.8h + MOV v12.d[0], v19.d[0] + MOV v12.d[1], v21.d[0] + MOV V14.16B , V4.16B -// VUZP.16 D12, D13 + rev64 v10.8h, v10.8h + MOV v11.d[0], v10.d[1] - UZP1 v19.8h, v12.8h, v12.8h - UZP2 v21.8h, v12.8h, v12.8h - MOV v12.d[0], v19.d[0] - MOV v12.d[1], v21.d[0] - SQADD v14.4s, v4.4s , v20.4s + rev64 v12.8h, v12.8h + MOV v13.d[0], v12.d[1] - rev64 v10.8h, v10.8h - MOV v11.d[0], v10.d[1] - SQADD v6.4s, v6.4s , v20.4s + sQshL v8.4s, v8.4s, v16.4s - rev64 v12.8h, v12.8h - MOV v13.d[0], v12.d[1] - sshR v14.4s, v14.4s, #16 + MOV V31.16B, V6.16B + LD2 { v4.4s, v5.4s}, [x8] + ADD x8, x8,#32 -// VUZP.16 D14, D15 - - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] - - sshR v6.4s, v6.4s, #16 - -// VUZP.16 D6, D7 - - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] - - mov v15.8b, v6.8b - sQshL v8.4s, v8.4s, v16.4s - - LD2 { v4.4s, v5.4s}, [x8] - ADD x8, x8, #32 - MOV v6.16b, v5.16b - sQshL v30.4s, v30.4s, v16.4s + MOV v6.16b, v5.16b + sQshL v30.4s, v30.4s, v16.4s // VUZP.16 D4, D5 - UZP1 v19.8h, v4.8h, v4.8h - UZP2 v21.8h, v4.8h, v4.8h - MOV v4.d[0], v19.d[0] - MOV v5.d[0], v21.d[0] + UZP1 v19.8h, v4.8h, v4.8h + UZP2 v21.8h, v4.8h, v4.8h + MOV v4.d[0], v19.d[0] + MOV v5.d[0], v21.d[0] - SQSUB v8.4s, v8.4s , v24.4s + SQSUB v8.4s, v8.4s , v24.4s // VUZP.16 D6, D7 - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] + UZP1 v19.8h, v6.8h, v6.8h + UZP2 v21.8h, v6.8h, v6.8h + MOV v6.d[0], v19.d[0] + MOV v7.d[0], v21.d[0] - SQSUB v22.4s, v30.4s , v22.4s - - sQshL v30.4s, v8.4s, #2 - - LD2 {v8.4h, v9.4h}, [x2] - ADD x2, x2, #16 - sQshL v22.4s, v22.4s, #2 - - SQADD v30.4s, v30.4s , v20.4s - SQADD v22.4s, v22.4s , v20.4s - - sshR v30.4s, v30.4s, #16 - -// VUZP.16 D30, D31 - - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] - - sshR v22.4s, v22.4s, #16 + SQSUB v22.4s, v30.4s , v22.4s -// VUZP.16 D22, D23 + MOV V30.16B, V8.16B - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] + LD2 {v8.4h, v9.4h}, [x2] + ADD x2, x2, #16 - mov v23.8b, v30.8b - CORE_LOOP: - ST1 {v14.h}[0], [x0] - ADD x0, x0, x9 - uMULL v30.4s, v0.4h, v9.4h - - ST1 {v22.h}[0], [x0] - ADD x0, x0, x9 - uMULL v28.4s, v2.4h, v8.4h - - ST1 {v14.h}[1], [x0] - ADD x0, x0, x9 - uMULL v26.4s, v0.4h, v8.4h - - ST1 {v22.h}[1], [x0] - ADD x0, x0, x9 - uMULL v24.4s, v2.4h, v9.4h - - ST1 {v14.h}[2], [x0] - ADD x0, x0, x9 - ushR v30.4s, v30.4s, #16 - - ST1 {v22.h}[2], [x0] - ADD x0, x0, x9 - ushR v28.4s, v28.4s, #16 - - ST1 {v14.h}[3], [x0] - ADD x0, x0, x9 - sMLAL v30.4s, v1.4h, v9.4h - - ST1 {v22.h}[3], [x0] - ADD x0, x0, x9 - sMLAL v28.4s, v3.4h, v8.4h - - ST1 {v15.h}[0], [x5] - ADD x5, x5, x10 - ushR v26.4s, v26.4s, #16 - - ST1 {v23.h}[0], [x5] - ADD x5, x5, x10 - ushR v24.4s, v24.4s, #16 - - ST1 {v15.h}[1], [x5] - ADD x5, x5, x10 - sMLAL v26.4s, v1.4h, v8.4h - - ST1 {v23.h}[1], [x5] - ADD x5, x5, x10 - sMLAL v24.4s, v3.4h, v9.4h - - ST1 {v15.h}[2], [x5] - ADD x5, x5, x10 - ADD v30.4s, v30.4s , v28.4s - - ST1 {v23.h}[2], [x5] - ADD x5, x5, x10 - NEG v30.4s, v30.4s - - ST1 {v15.h}[3], [x5] - ADD x5, x5, x10 - - ST1 {v23.h}[3], [x5] - ADD x5, x5, x10 - SUB v28.4s, v24.4s , v26.4s + ST1 {V14.S}[0], [x0] + ADD x0, x0, x9 + ST1 {V22.S}[0], [x0] + ADD x0, x0, x9 - mov v26.16b, v30.16b - uMULL v22.4s, v4.4h, v8.4h + ST1 {V14.S}[1], [x0] + ADD x0, x0, x9 - mov v24.16b, v28.16b + + ST1 {V22.S}[1], [x0] + ADD x0, x0, x9 + + + ST1 {V14.S}[2], [x0] + ADD x0, x0, x9 + + + ST1 {V22.S}[2], [x0] + ADD x0, x0, x9 + + + ST1 {V14.S}[3], [x0] + ADD x0, x0, x9 + + + ST1 {V22.S}[3], [x0] + ADD x0, x0, x9 + + + ST1 {V31.S}[0], [x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[0], [x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[1], [x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[1], [x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[2], [x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[2], [x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[3], [x5] + ADD x5, x5, x10 + + ST1 {V30.S}[3], [x5] + ADD x5, x5, x10 + + + uMULL v30.4s, v0.4h, v9.4h + uMULL v28.4s, v2.4h, v8.4h + uMULL v26.4s, v0.4h, v8.4h + uMULL v24.4s, v2.4h, v9.4h + ushR v30.4s, v30.4s,#16 + ushR v28.4s, v28.4s,#16 + sMLAL v30.4s, v1.4h, v9.4h + sMLAL v28.4s, v3.4h, v8.4h + ushR v26.4s, v26.4s,#16 + ushR v24.4s, v24.4s,#16 + sMLAL v26.4s, v1.4h, v8.4h + sMLAL v24.4s, v3.4h, v9.4h + ADD v30.4s, v30.4s , v28.4s + NEG v30.4s, v30.4s + SUB v28.4s, v24.4s , v26.4s + + mov v26.16b, v30.16b + uMULL v22.4s, v4.4h, v8.4h + + mov v24.16b, v28.16b // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - uMULL v2.4s, v24.4h, v18.4h - uMULL v0.4s, v26.4h, v18.4h + uMULL v2.4s, v24.4h, v18.4h + uMULL v0.4s, v26.4h, v18.4h - ushR v22.4s, v22.4s, #16 - sMLAL v22.4s, v5.4h, v8.4h + ushR v22.4s, v22.4s,#16 + sMLAL v22.4s, v5.4h, v8.4h - ushR v2.4s, v2.4s, #16 - ushR v0.4s, v0.4s, #16 - sMLAL v2.4s, v25.4h, v18.4h - sMLAL v0.4s, v27.4h, v18.4h + ushR v2.4s, v2.4s,#16 + ushR v0.4s, v0.4s,#16 + sMLAL v2.4s, v25.4h, v18.4h + sMLAL v0.4s, v27.4h, v18.4h - uMULL v24.4s, v4.4h, v9.4h - uMULL v26.4s, v6.4h, v8.4h + uMULL v24.4s, v4.4h, v9.4h + uMULL v26.4s, v6.4h, v8.4h - NEG v2.4s, v2.4s - ADD v28.4s, v28.4s , v0.4s - ADD v30.4s, v30.4s , v2.4s + NEG v2.4s, v2.4s + ADD v28.4s, v28.4s , v0.4s + ADD v30.4s, v30.4s , v2.4s - uMULL v0.4s, v6.4h, v9.4h - sshR v24.4s, v24.4s, #16 - sMLAL v24.4s, v5.4h, v9.4h - sshR v26.4s, v26.4s, #16 - sshR v0.4s, v0.4s, #16 - sMLAL v26.4s, v7.4h, v8.4h - sMLAL v0.4s, v7.4h, v9.4h + uMULL v0.4s, v6.4h, v9.4h + sshR v24.4s, v24.4s,#16 + sMLAL v24.4s, v5.4h, v9.4h + sshR v26.4s, v26.4s,#16 + sshR v0.4s, v0.4s,#16 + sMLAL v26.4s, v7.4h, v8.4h + sMLAL v0.4s, v7.4h, v9.4h - ADD v22.4s, v22.4s , v0.4s + ADD v22.4s, v22.4s , v0.4s - NEG v22.4s, v22.4s - SUB v24.4s, v26.4s , v24.4s + NEG v22.4s, v22.4s + SUB v24.4s, v26.4s , v24.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v14.4s, w11 - SQADD v28.4s, v28.4s , v14.4s + //sxtw x11,w11 + MOV w11, w26 + dup v14.4s,w11 + SQADD v28.4s, v28.4s , v14.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v0.4s, w11 - sQshL v28.4s, v28.4s, v0.4s + //sxtw x11,w11 + MOV w11, w25 + dup v0.4s,w11 + sQshL v28.4s, v28.4s, v0.4s - mov v0.16b, v22.16b - mov v14.16b, v24.16b + mov v0.16b, v22.16b + mov v14.16b, v24.16b // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] // VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] + UZP1 v19.8h, v22.8h, v22.8h + UZP2 v21.8h, v22.8h, v22.8h + MOV v22.d[0], v19.d[0] + MOV v23.d[0], v21.d[0] - uMULL v8.4s, v24.4h, v18.4h - uMULL v26.4s, v22.4h, v18.4h + uMULL v8.4s, v24.4h, v18.4h + uMULL v26.4s, v22.4h, v18.4h - NEG v2.4s, v30.4s + NEG v2.4s, v30.4s // VUZP.16 D30, D31 - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] + UZP1 v19.8h, v30.8h, v30.8h + UZP2 v21.8h, v30.8h, v30.8h + MOV v30.d[0], v19.d[0] + MOV v30.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v3.d[0], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v3.d[0], v21.d[0] - uMULL v4.4s, v30.4h, v12.4h - uMULL v6.4s, v2.4h, v13.4h + uMULL v4.4s, v30.4h, v12.4h + uMULL v6.4s, v2.4h, v13.4h - ushR v8.4s, v8.4s, #16 - ushR v26.4s, v26.4s, #16 + ushR v8.4s, v8.4s,#16 + ushR v26.4s, v26.4s,#16 - sMLAL v8.4s, v25.4h, v18.4h - sMLAL v26.4s, v23.4h, v18.4h + sMLAL v8.4s, v25.4h, v18.4h + sMLAL v26.4s, v23.4h, v18.4h - ushR v4.4s, v4.4s, #16 - ushR v6.4s, v6.4s, #16 + ushR v4.4s, v4.4s,#16 + ushR v6.4s, v6.4s,#16 - MOV v19.d[0], v30.d[1] + MOV v19.d[0], v30.d[1] - sMLAL v4.4s, v19.4h, v12.4h - sMLAL v6.4s, v3.4h, v13.4h + sMLAL v4.4s, v19.4h, v12.4h + sMLAL v6.4s, v3.4h, v13.4h - NEG v8.4s, v8.4s - ADD v14.4s, v14.4s , v26.4s - ADD v0.4s, v0.4s , v8.4s + NEG v8.4s, v8.4s + ADD v14.4s, v14.4s , v26.4s + ADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v8.4s, w11 - SQADD v0.4s, v0.4s , v8.4s + //sxtw x11,w11 + MOV w11, w26 + dup v8.4s,w11 + SQADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v26.4s, w11 - sQshL v0.4s, v0.4s, v26.4s - mov v26.16b, v28.16b + //sxtw x11,w11 + MOV w11, w25 + dup v26.4s,w11 + sQshL v0.4s, v0.4s, v26.4s + mov v26.16b, v28.16b - LD2 { v28.4s, v29.4s}, [x4] - MOV v30.16b, v29.16b - MOV v29.d[0], v28.d[1] + LD2 { v28.4s, v29.4s}, [x4] + MOV v30.16b, v29.16b + MOV v29.d[0], v28.d[1] // VZIP.32 Q13, Q0 - ZIP1 v19.4s, v26.4s, v0.4s - ZIP2 v0.4s, v26.4s, v0.4s - MOV v26.16b, v19.16b + ZIP1 v19.4s, v26.4s, v0.4s + ZIP2 v0.4s, v26.4s, v0.4s + MOV v26.16b, v19.16b - ST1 { v26.4s}, [x4] - ADD x4, x4, #16 - ST1 { v0.4s}, [x4] - ADD x4, x4, #16 + ST1 { v26.4s}, [x4] + ADD x4, x4,#16 + ST1 { v0.4s}, [x4] + ADD x4, x4,#16 - movi v1.2s, #0 + movi v1.2s, #0 // VADDL.S16 Q0, D13, D1 - SADDL v0.4s, v13.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v13.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v26.2d, v28.2s, v0.2s - Sqxtn v8.2s, v26.2d - sMULL v26.2d, v29.2s, v1.2s - Sqxtn v9.2s, v26.2d - MOV v8.d[1], v9.d[0] - movi v1.2s, #0 + sMULL v26.2d, v28.2s, v0.2s + Sqxtn v8.2s, v26.2d + sMULL v26.2d, v29.2s, v1.2s + Sqxtn v9.2s, v26.2d + MOV v8.d[1], v9.d[0] + movi v1.2s, #0 //VADDL.S16 Q0, D12, D1 - SADDL v0.4s, v12.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v12.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v24.2d, v28.2s, v0.2s - Sqxtn v26.2s, v24.2d - sMULL v24.2d, v29.2s, v1.2s - Sqxtn v27.2s, v24.2d - MOV v26.d[1], v27.d[0] - sQshL v4.4s, v4.4s, v16.4s - sQshL v6.4s, v6.4s, v16.4s + sMULL v24.2d, v28.2s, v0.2s + Sqxtn v26.2s, v24.2d + sMULL v24.2d, v29.2s, v1.2s + Sqxtn v27.2s, v24.2d + MOV v26.d[1], v27.d[0] + sQshL v4.4s, v4.4s, v16.4s + sQshL v6.4s, v6.4s, v16.4s - SQSUB v4.4s, v4.4s , v8.4s - SQSUB v6.4s, v6.4s , v26.4s + SQSUB v4.4s, v4.4s , v8.4s + SQSUB v6.4s, v6.4s , v26.4s - NEG v26.4s, v14.4s + NEG v26.4s, v14.4s // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - movi v1.2s, #0 - //VADDL.S16 Q0, D10, D1 - SADDL v0.4s, v10.4h, v1.4h - MOV v1.d[0], v0.d[1] + movi v1.2s, #0 + //VADDL.S16 Q0, D10, D1 + SADDL v0.4s, v10.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v22.2d, v30.2s, v0.2s - Sqxtn v24.2s, v22.2d - sMULL2 v22.2d, v30.4s, v0.4s - Sqxtn v25.2s, v22.2d - MOV v24.d[1], v25.d[0] - movi v1.2s, #0 + sMULL v22.2d, v30.2s, v0.2s + Sqxtn v24.2s, v22.2d + sMULL2 v22.2d, v30.4s, v0.4s + Sqxtn v25.2s, v22.2d + MOV v24.d[1], v25.d[0] + movi v1.2s, #0 //VADDL.S16 Q0, D11, D1 - SADDL v0.4s, v11.4h, v1.4h + SADDL v0.4s, v11.4h, v1.4h - sMULL v8.2d, v30.2s, v0.2s - Sqxtn v22.2s, v8.2d - sMULL2 v8.2d, v30.4s, v0.4s - Sqxtn v23.2s, v8.2d - MOV v22.d[1], v23.d[0] + sMULL v8.2d, v30.2s, v0.2s + Sqxtn v22.2s, v8.2d + sMULL2 v8.2d, v30.4s, v0.4s + Sqxtn v23.2s, v8.2d + MOV v22.d[1], v23.d[0] // VUZP.16 D14, D15 - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + UZP1 v19.8h, v14.8h, v14.8h + UZP2 v21.8h, v14.8h, v14.8h + MOV v14.d[0], v19.d[0] + MOV v15.d[0], v21.d[0] - uMULL v8.4s, v26.4h, v11.4h - uMULL v30.4s, v14.4h, v10.4h + uMULL v8.4s, v26.4h, v11.4h + uMULL v30.4s, v14.4h, v10.4h - LD2 { v0.4s, v1.4s}, [x1] - MOV v2.16b, v1.16b - ADD X1, X1, x12 + LD2 { v0.4s, v1.4s}, [x1] + MOV v2.16b, v1.16b + ADD X1, X1, x12 // VUZP.16 D0, D1 - UZP1 v19.8h, v0.8h, v0.8h - UZP2 v21.8h, v0.8h, v0.8h - MOV v0.d[0], v19.d[0] - MOV v0.d[1], v21.d[0] + UZP1 v19.8h, v0.8h, v0.8h + UZP2 v21.8h, v0.8h, v0.8h + MOV v0.d[0], v19.d[0] + MOV v0.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v2.d[1], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v2.d[1], v21.d[0] - ushR v8.4s, v8.4s, #16 + ushR v8.4s, v8.4s,#16 - rev64 v0.8h, v0.8h - MOV v1.d[0], v0.d[1] - ushR v30.4s, v30.4s, #16 + rev64 v0.8h, v0.8h + MOV v1.d[0], v0.d[1] + ushR v30.4s, v30.4s,#16 - rev64 v2.8h, v2.8h - MOV v3.d[0], v2.d[1] - sMLAL v8.4s, v27.4h, v11.4h + rev64 v2.8h, v2.8h + MOV v3.d[0], v2.d[1] + sMLAL v8.4s, v27.4h, v11.4h - sMLAL v30.4s, v15.4h, v10.4h + sMLAL v30.4s, v15.4h, v10.4h + + LD2 { v10.4s, v11.4s}, [x6] + add X6, x6, x12 + MOV v12.16b, v11.16b - LD2 { v10.4s, v11.4s}, [x6] - add X6, x6, x12 - MOV v12.16b, v11.16b - sQshL v4.4s, v4.4s, #2 //VUZP.16 D10, D11 - UZP1 v19.8h, v10.8h, v10.8h - UZP2 v21.8h, v10.8h, v10.8h - MOV v10.d[0], v19.d[0] - MOV v10.d[1], v21.d[0] + UZP1 v19.8h, v10.8h, v10.8h + UZP2 v21.8h, v10.8h, v10.8h + MOV v10.d[0], v19.d[0] + MOV v10.d[1], v21.d[0] + - sQshL v6.4s, v6.4s, #2 // VUZP.16 D12, D13 - UZP1 v19.8h, v12.8h, v12.8h - UZP2 v21.8h, v12.8h, v12.8h - MOV v12.d[0], v19.d[0] - MOV v12.d[1], v21.d[0] + UZP1 v19.8h, v12.8h, v12.8h + UZP2 v21.8h, v12.8h, v12.8h + MOV v12.d[0], v19.d[0] + MOV v12.d[1], v21.d[0] - SQADD v14.4s, v4.4s , v20.4s - rev64 v10.8h, v10.8h - MOV v11.d[0], v10.d[1] - SQADD v6.4s, v6.4s , v20.4s + MOV V14.16B, V4.16B - rev64 v12.8h, v12.8h - MOV v13.d[0], v12.d[1] - sshR v14.4s, v14.4s, #16 - -// VUZP.16 D14, D15 - - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + rev64 v10.8h, v10.8h + MOV v11.d[0], v10.d[1] - sshR v6.4s, v6.4s, #16 + rev64 v12.8h, v12.8h + MOV v13.d[0], v12.d[1] + + sQshL v8.4s, v8.4s, v16.4s + + LD2 { v4.4s, v5.4s}, [x8] + ADD x8, x8, #32 + + MOV V31.16B, V6.16B + MOV v6.16b, v5.16b + + sQshL v30.4s, v30.4s, v16.4s + + + UZP1 v19.8h, v4.8h, v4.8h + UZP2 v21.8h, v4.8h, v4.8h + MOV v4.d[0], v19.d[0] + MOV v5.d[0], v21.d[0] + + + SQSUB v8.4s, v8.4s , v24.4s // VUZP.16 D6, D7 - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] + UZP1 v19.8h, v6.8h, v6.8h + UZP2 v21.8h, v6.8h, v6.8h + MOV v6.d[0], v19.d[0] + MOV v7.d[0], v21.d[0] + + SQSUB v22.4s, v30.4s , v22.4s + + MOV V30.16B , V8.16B + + LD2 {v8.4h, v9.4h}, [x2] + ADD x2, x2,#16 - mov v15.8b, v6.8b - sQshL v8.4s, v8.4s, v16.4s - LD2 { v4.4s, v5.4s}, [x8] - ADD x8, x8, #32 - MOV v6.16b, v5.16b - - sQshL v30.4s, v30.4s, v16.4s - -// VUZP.16 D4, D5 - - UZP1 v19.8h, v4.8h, v4.8h - UZP2 v21.8h, v4.8h, v4.8h - MOV v4.d[0], v19.d[0] - MOV v5.d[0], v21.d[0] - - - SQSUB v8.4s, v8.4s , v24.4s - -// VUZP.16 D6, D7 - - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] - - - SQSUB v22.4s, v30.4s , v22.4s - - sQshL v30.4s, v8.4s, #2 - - LD2 {v8.4h, v9.4h}, [x2] - ADD x2, x2, #16 - sQshL v22.4s, v22.4s, #2 - - SQADD v30.4s, v30.4s , v20.4s - SQADD v22.4s, v22.4s , v20.4s - - sshR v30.4s, v30.4s, #16 - -// VUZP.16 D30, D31 - - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] - - - sshR v22.4s, v22.4s, #16 - - -// VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] - - - mov v23.8b, v30.8b SUBS x3, x3, #1 BNE CORE_LOOP @@ -1190,844 +1114,765 @@ CORE_LOOP: EPILOGUE: - ST1 {v14.h}[0], [x0] - ADD x0, x0, x9 - uMULL v30.4s, v0.4h, v9.4h - - ST1 {v22.h}[0], [x0] - ADD x0, x0, x9 - uMULL v28.4s, v2.4h, v8.4h - - ST1 {v14.h}[1], [x0] - ADD x0, x0, x9 - uMULL v26.4s, v0.4h, v8.4h - - ST1 {v22.h}[1], [x0] - ADD x0, x0, x9 - uMULL v24.4s, v2.4h, v9.4h - - ST1 {v14.h}[2], [x0] - ADD x0, x0, x9 - ushR v30.4s, v30.4s, #16 - - ST1 {v22.h}[2], [x0] - ADD x0, x0, x9 - ushR v28.4s, v28.4s, #16 - - ST1 {v14.h}[3], [x0] - ADD x0, x0, x9 - sMLAL v30.4s, v1.4h, v9.4h - - ST1 {v22.h}[3], [x0] - ADD x0, x0, x9 - sMLAL v28.4s, v3.4h, v8.4h - - ST1 {v15.h}[0], [x5] - ADD x5, x5, x10 - ushR v26.4s, v26.4s, #16 - - ST1 {v23.h}[0], [x5] - ADD x5, x5, x10 - ushR v24.4s, v24.4s, #16 - - ST1 {v15.h}[1], [x5] - ADD x5, x5, x10 - sMLAL v26.4s, v1.4h, v8.4h - - ST1 {v23.h}[1], [x5] - ADD x5, x5, x10 - sMLAL v24.4s, v3.4h, v9.4h - - ST1 {v15.h}[2], [x5] - ADD x5, x5, x10 - ADD v30.4s, v30.4s , v28.4s - - ST1 {v23.h}[2], [x5] - ADD x5, x5, x10 - NEG v30.4s, v30.4s - - ST1 {v15.h}[3], [x5] - ADD x5, x5, x10 + ST1 {V14.S}[0],[x0] + ADD x0, x0, x9 - ST1 {v23.h}[3], [x5] - ADD x5, x5, x10 - SUB v28.4s, v24.4s , v26.4s + ST1 {V22.S}[0],[x0] + ADD x0, x0, x9 - uMULL v22.4s, v4.4h, v8.4h - mov v26.16b, v30.16b - mov v24.16b, v28.16b + ST1 {V14.S}[1],[x0] + ADD x0, x0, x9 - mov v26.16b, v30.16b - mov v24.16b, v28.16b + + ST1 {V22.S}[1],[x0] + ADD x0, x0, x9 + + + ST1 {V14.S}[2],[x0] + ADD x0, x0, x9 + + + ST1 {V22.S}[2],[x0] + ADD x0, x0, x9 + + + ST1 {V14.S}[3],[x0] + ADD x0, x0, x9 + + + ST1 {V22.S}[3],[x0] + ADD x0, x0, x9 + + + ST1 {V31.S}[0],[x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[0],[x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[1],[x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[1],[x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[2],[x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[2],[x5] + ADD x5, x5, x10 + + + ST1 {V31.S}[3],[x5] + ADD x5, x5, x10 + + + ST1 {V30.S}[3],[x5] + ADD x5, x5, x10 + + + uMULL v30.4s, v0.4h, v9.4h + uMULL v28.4s, v2.4h, v8.4h + uMULL v26.4s, v0.4h, v8.4h + uMULL v24.4s, v2.4h, v9.4h + ushR v30.4s, v30.4s,#16 + ushR v28.4s, v28.4s,#16 + sMLAL v30.4s, v1.4h, v9.4h + sMLAL v28.4s, v3.4h, v8.4h + ushR v26.4s, v26.4s,#16 + ushR v24.4s, v24.4s,#16 + sMLAL v26.4s, v1.4h, v8.4h + sMLAL v24.4s, v3.4h, v9.4h + ADD v30.4s, v30.4s , v28.4s + NEG v30.4s, v30.4s + SUB v28.4s, v24.4s , v26.4s + + + uMULL v22.4s, v4.4h, v8.4h + mov v26.16b, v30.16b + mov v24.16b, v28.16b + + mov v26.16b, v30.16b + mov v24.16b, v28.16b //VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] - uMULL v2.4s, v24.4h, v18.4h - uMULL v0.4s, v26.4h, v18.4h + uMULL v2.4s, v24.4h, v18.4h + uMULL v0.4s, v26.4h, v18.4h - ushR v22.4s, v22.4s, #16 - sMLAL v22.4s, v5.4h, v8.4h + ushR v22.4s, v22.4s,#16 + sMLAL v22.4s, v5.4h, v8.4h - ushR v2.4s, v2.4s, #16 - ushR v0.4s, v0.4s, #16 - sMLAL v2.4s, v25.4h, v18.4h - sMLAL v0.4s, v27.4h, v18.4h + ushR v2.4s, v2.4s,#16 + ushR v0.4s, v0.4s,#16 + sMLAL v2.4s, v25.4h, v18.4h + sMLAL v0.4s, v27.4h, v18.4h - uMULL v24.4s, v4.4h, v9.4h - uMULL v26.4s, v6.4h, v8.4h + uMULL v24.4s, v4.4h, v9.4h + uMULL v26.4s, v6.4h, v8.4h - NEG v2.4s, v2.4s - ADD v28.4s, v28.4s , v0.4s - ADD v30.4s, v30.4s , v2.4s + NEG v2.4s, v2.4s + ADD v28.4s, v28.4s , v0.4s + ADD v30.4s, v30.4s , v2.4s - uMULL v0.4s, v6.4h, v9.4h - sshR v24.4s, v24.4s, #16 - sMLAL v24.4s, v5.4h, v9.4h - sshR v26.4s, v26.4s, #16 - sshR v0.4s, v0.4s, #16 - sMLAL v26.4s, v7.4h, v8.4h - sMLAL v0.4s, v7.4h, v9.4h + uMULL v0.4s, v6.4h, v9.4h + sshR v24.4s, v24.4s,#16 + sMLAL v24.4s, v5.4h, v9.4h + sshR v26.4s, v26.4s,#16 + sshR v0.4s, v0.4s,#16 + sMLAL v26.4s, v7.4h, v8.4h + sMLAL v0.4s, v7.4h, v9.4h - ADD v22.4s, v22.4s , v0.4s - NEG v22.4s, v22.4s - SUB v24.4s, v26.4s , v24.4s + ADD v22.4s, v22.4s , v0.4s + NEG v22.4s, v22.4s + SUB v24.4s, v26.4s , v24.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v14.4s, w11 - SQADD v28.4s, v28.4s , v14.4s + //sxtw x11,w11 + MOV w11, w26 + dup v14.4s,w11 + SQADD v28.4s, v28.4s , v14.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v0.4s, w11 - sQshL v28.4s, v28.4s, v0.4s + //sxtw x11,w11 + MOV w11, w25 + dup v0.4s,w11 + sQshL v28.4s, v28.4s, v0.4s - mov v0.16b, v22.16b - mov v14.16b, v24.16b + mov v0.16b, v22.16b + mov v14.16b, v24.16b // VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] + UZP1 v19.8h, v22.8h, v22.8h + UZP2 v21.8h, v22.8h, v22.8h + MOV v22.d[0], v19.d[0] + MOV v23.d[0], v21.d[0] // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] - uMULL v8.4s, v24.4h, v18.4h - uMULL v26.4s, v22.4h, v18.4h + uMULL v8.4s, v24.4h, v18.4h + uMULL v26.4s, v22.4h, v18.4h - NEG v2.4s, v30.4s + NEG v2.4s, v30.4s // VUZP.16 D30, D31 - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] + UZP1 v19.8h, v30.8h, v30.8h + UZP2 v21.8h, v30.8h, v30.8h + MOV v30.d[0], v19.d[0] + MOV v30.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v3.d[0], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v3.d[0], v21.d[0] - uMULL v4.4s, v30.4h, v12.4h - uMULL v6.4s, v2.4h, v13.4h + uMULL v4.4s, v30.4h, v12.4h + uMULL v6.4s, v2.4h, v13.4h - ushR v8.4s, v8.4s, #16 - ushR v26.4s, v26.4s, #16 + ushR v8.4s, v8.4s,#16 + ushR v26.4s, v26.4s,#16 - sMLAL v8.4s, v25.4h, v18.4h - sMLAL v26.4s, v23.4h, v18.4h + sMLAL v8.4s, v25.4h, v18.4h + sMLAL v26.4s, v23.4h, v18.4h - ushR v4.4s, v4.4s, #16 - ushR v6.4s, v6.4s, #16 + ushR v4.4s, v4.4s,#16 + ushR v6.4s, v6.4s,#16 - MOV v19.d[0], v30.d[1] + MOV v19.d[0], v30.d[1] - sMLAL v4.4s, v19.4h, v12.4h - sMLAL v6.4s, v3.4h, v13.4h + sMLAL v4.4s, v19.4h, v12.4h + sMLAL v6.4s, v3.4h, v13.4h - NEG v8.4s, v8.4s - ADD v14.4s, v14.4s , v26.4s - ADD v0.4s, v0.4s , v8.4s + NEG v8.4s, v8.4s + ADD v14.4s, v14.4s , v26.4s + ADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v8.4s, w11 - SQADD v0.4s, v0.4s , v8.4s + //sxtw x11,w11 + MOV w11, w26 + dup v8.4s,w11 + SQADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v26.4s, w11 - sQshL v0.4s, v0.4s, v26.4s + //sxtw x11,w11 + MOV w11, w25 + dup v26.4s,w11 + sQshL v0.4s, v0.4s, v26.4s - mov v26.16b, v28.16b + mov v26.16b, v28.16b - LD2 { v28.4s, v29.4s}, [x4] - MOV v30.16b, v29.16b - MOV v29.d[0], v28.d[1] + LD2 { v28.4s, v29.4s}, [x4] + MOV v30.16b, v29.16b + MOV v29.d[0], v28.d[1] // VZIP.32 Q13, Q0 - ZIP1 v19.4s, v26.4s, v0.4s - ZIP2 v0.4s, v26.4s, v0.4s - MOV v26.16b, v19.16b + ZIP1 v19.4s, v26.4s, v0.4s + ZIP2 v0.4s, v26.4s, v0.4s + MOV v26.16b, v19.16b - ST1 { v26.4s}, [x4], #16 - ST1 { v0.4s}, [x4], #16 + ST1 { v26.4s}, [x4],#16 + ST1 { v0.4s}, [x4],#16 - movi v1.2s, #0 + movi v1.2s, #0 // VADDL.S16 Q0, D13, D1 - SADDL v0.4s, v13.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v13.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v26.2d, v28.2s, v0.2s - Sqxtn v8.2s, v26.2d - sMULL v26.2d, v29.2s, v1.2s - Sqxtn v9.2s, v26.2d - MOV v8.d[1], v9.d[0] - movi v1.2s, #0 + sMULL v26.2d, v28.2s, v0.2s + Sqxtn v8.2s, v26.2d + sMULL v26.2d, v29.2s, v1.2s + Sqxtn v9.2s, v26.2d + MOV v8.d[1], v9.d[0] + movi v1.2s, #0 // VADDL.S16 Q0, D12, D1 - SADDL v0.4s, v12.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v12.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v24.2d, v28.2s, v0.2s - Sqxtn v26.2s, v24.2d - sMULL v24.2d, v29.2s, v1.2s - Sqxtn v27.2s, v24.2d - MOV v26.d[1], v27.d[0] + sMULL v24.2d, v28.2s, v0.2s + Sqxtn v26.2s, v24.2d + sMULL v24.2d, v29.2s, v1.2s + Sqxtn v27.2s, v24.2d + MOV v26.d[1], v27.d[0] - sQshL v4.4s, v4.4s, v16.4s - sQshL v6.4s, v6.4s, v16.4s + sQshL v4.4s, v4.4s, v16.4s + sQshL v6.4s, v6.4s, v16.4s - SQSUB v4.4s, v4.4s , v8.4s - SQSUB v6.4s, v6.4s , v26.4s + SQSUB v4.4s, v4.4s , v8.4s + SQSUB v6.4s, v6.4s , v26.4s - NEG v26.4s, v14.4s + NEG v26.4s, v14.4s // VUZP.16 D14, D15 - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + UZP1 v19.8h, v14.8h, v14.8h + UZP2 v21.8h, v14.8h, v14.8h + MOV v14.d[0], v19.d[0] + MOV v15.d[0], v21.d[0] -// VUZP.16 D26, D27 + // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - movi v1.2s, #0 + movi v1.2s, #0 //VADDL.S16 Q0, D10, D1 - SADDL v0.4s, v10.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v10.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v22.2d, v30.2s, v0.2s - Sqxtn v24.2s, v22.2d - sMULL2 v22.2d, v30.4s, v0.4s - Sqxtn v25.2s, v22.2d - MOV v24.d[1], v25.d[0] - movi v1.2s, #0 + sMULL v22.2d, v30.2s, v0.2s + Sqxtn v24.2s, v22.2d + sMULL2 v22.2d, v30.4s, v0.4s + Sqxtn v25.2s, v22.2d + MOV v24.d[1], v25.d[0] + movi v1.2s, #0 //VADDL.S16 Q0, D11, D1 - SADDL v0.4s, v11.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v11.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v8.2d, v30.2s, v0.2s - Sqxtn v22.2s, v8.2d - sMULL2 v8.2d, v30.4s, v0.4s - Sqxtn v23.2s, v8.2d - MOV v22.d[1], v23.d[0] + sMULL v8.2d, v30.2s, v0.2s + Sqxtn v22.2s, v8.2d + sMULL2 v8.2d, v30.4s, v0.4s + Sqxtn v23.2s, v8.2d + MOV v22.d[1], v23.d[0] - uMULL v8.4s, v26.4h, v11.4h - uMULL v30.4s, v14.4h, v10.4h + uMULL v8.4s, v26.4h, v11.4h + uMULL v30.4s, v14.4h, v10.4h - ushR v8.4s, v8.4s, #16 + ushR v8.4s, v8.4s,#16 - ushR v30.4s, v30.4s, #16 + ushR v30.4s, v30.4s,#16 - sMLAL v8.4s, v27.4h, v11.4h + sMLAL v8.4s, v27.4h, v11.4h - sMLAL v30.4s, v15.4h, v10.4h + sMLAL v30.4s, v15.4h, v10.4h - sQshL v4.4s, v4.4s, #2 - sQshL v6.4s, v6.4s, #2 + MOV V14.16B, V4.16B - SQADD v14.4s, v4.4s , v20.4s - SQADD v6.4s, v6.4s , v20.4s + sQshL v8.4s, v8.4s, v16.4s - sshR v14.4s, v14.4s, #16 + sQshL v30.4s, v30.4s, v16.4s -// VUZP.16 D14, D15 + SQSUB v8.4s, v8.4s , v24.4s - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + SQSUB v22.4s, v30.4s , v22.4s - sshR v6.4s, v6.4s, #16 - -// VUZP.16 D6, D7 - - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] - - mov v15.8b, v6.8b - sQshL v8.4s, v8.4s, v16.4s - - sQshL v30.4s, v30.4s, v16.4s - - SQSUB v8.4s, v8.4s , v24.4s - - SQSUB v22.4s, v30.4s , v22.4s - - sQshL v30.4s, v8.4s, #2 - - sQshL v22.4s, v22.4s, #2 - - SQADD v30.4s, v30.4s , v20.4s - SQADD v22.4s, v22.4s , v20.4s - - sshR v30.4s, v30.4s, #16 - - //VUZP.16 D30, D31 - - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] - - sshR v22.4s, v22.4s, #16 - -// VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] - - mov v23.8b, v30.8b + MOV V30.16B , V8.16B - ST1 {v14.h}[0], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[0], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[1], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[1], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[2], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[2], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[3], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[3], [x0] - ADD x0, x0, x9 - ST1 {v15.h}[0], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[0], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[1], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[1], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[2], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[2], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[3], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[3], [x5] - ADD x5, x5, x10 + ST1 {V14.S}[0],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[0],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[1],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[1],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[2],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[2],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[3],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[3],[x0] + ADD x0, x0, x9 + ST1 {V6.S}[0],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[0],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[1],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[1],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[2],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[2],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[3],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[3],[x5] + ADD x5, x5, x10 ARM_EPILOGUE: ARM_LOOP: - LD2 { v0.4s, v1.4s}, [x1] - MOV v2.16b, v1.16b + LD2 { v0.4s, v1.4s}, [x1] + MOV v2.16b, v1.16b //VUZP.16 D0, D1 - UZP1 v19.8h, v0.8h, v0.8h - UZP2 v21.8h, v0.8h, v0.8h - MOV v0.d[0], v19.d[0] - MOV v0.d[1], v21.d[0] + UZP1 v19.8h, v0.8h, v0.8h + UZP2 v21.8h, v0.8h, v0.8h + MOV v0.d[0], v19.d[0] + MOV v0.d[1], v21.d[0] - //VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v2.d[1], v21.d[0] + //VUZP.16 D2, D3 + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v2.d[1], v21.d[0] - rev64 v0.8h, v0.8h - MOV v1.d[0], v0.d[1] - rev64 v2.8h, v2.8h - MOV v3.d[0], v2.d[1] + rev64 v0.8h, v0.8h + MOV v1.d[0], v0.d[1] + rev64 v2.8h, v2.8h + MOV v3.d[0], v2.d[1] - LD2 {v8.4h, v9.4h}, [x2] - ADD x2, x2, #16 + LD2 {v8.4h, v9.4h}, [x2] + ADD x2, x2,#16 - LD2 {v4.2s, v5.2s}, [x8] - ADD x8, x8, #16 - MOV v6.16b, v5.16b - movi v5.2s, #0x00000000 - movi v7.2s, #0x00000000 + LD2 {v4.2s, v5.2s}, [x8] + ADD x8, x8,#16 + MOV v6.16b, v5.16b + movi v5.2s, #0x00000000 + movi v7.2s, #0x00000000 - LD1 {v5.s}[0], [x8], #4 - LD1 {v7.s}[0], [x8] + LD1 {v5.s}[0],[x8],#4 + LD1 {v7.s}[0],[x8] MOV x12, #16 - MOV v4.d[1], v5.d[0] - MOV v6.d[1], v7.d[0] + MOV v4.d[1], v5.d[0] + MOV v6.d[1], v7.d[0] // VUZP.16 D4, D5 - UZP1 v19.8h, v4.8h, v4.8h - UZP2 v21.8h, v4.8h, v4.8h - MOV v4.d[0], v19.d[0] - MOV v5.d[0], v21.d[0] + UZP1 v19.8h, v4.8h, v4.8h + UZP2 v21.8h, v4.8h, v4.8h + MOV v4.d[0], v19.d[0] + MOV v5.d[0], v21.d[0] // VUZP.16 D6, D7 - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] + UZP1 v19.8h, v6.8h, v6.8h + UZP2 v21.8h, v6.8h, v6.8h + MOV v6.d[0], v19.d[0] + MOV v7.d[0], v21.d[0] ADD x6, x6, #16 MOV x12, #-4 - LD2 {v11.2s, v12.2s}, [x6] - ADD x6, x6, x12 - MOV v13.16b, v12.16b + LD2 {v11.2s, v12.2s}, [x6] + ADD x6, x6, x12 + MOV v13.16b, v12.16b - movi v10.2s, #0x00000000 + movi v10.2s, #0x00000000 - LD1 {v12.s}[1], [x6] - ADD x6, x6, x12 - LD1 {v10.s}[1], [x6] - ADD x6, x6, x12 - LD1 {v12.s}[0], [x6] - ADD x6, x6, x12 + LD1 {v12.s}[1],[x6] + ADD x6, x6, x12 + LD1 {v10.s}[1],[x6] + ADD x6, x6, x12 + LD1 {v12.s}[0],[x6] + ADD x6, x6, x12 - MOV v10.d[1], v11.d[0] - MOV v12.d[1], v13.d[0] + MOV v10.d[1], v11.d[0] + MOV v12.d[1], v13.d[0] //VUZP.16 D10, D11 - UZP1 v19.8h, v10.8h, v10.8h - UZP2 v21.8h, v10.8h, v10.8h - MOV v10.d[0], v19.d[0] - MOV v10.d[1], v21.d[0] + UZP1 v19.8h, v10.8h, v10.8h + UZP2 v21.8h, v10.8h, v10.8h + MOV v10.d[0], v19.d[0] + MOV v10.d[1], v21.d[0] - //VUZP.16 D12, D13 + //VUZP.16 D12, D13 - UZP1 v19.8h, v12.8h, v12.8h - UZP2 v21.8h, v12.8h, v12.8h - MOV v12.d[0], v19.d[0] - MOV v12.d[1], v21.d[0] + UZP1 v19.8h, v12.8h, v12.8h + UZP2 v21.8h, v12.8h, v12.8h + MOV v12.d[0], v19.d[0] + MOV v12.d[1], v21.d[0] - rev64 v10.8h, v10.8h - MOV v11.d[0], v10.d[1] - rev64 v12.8h, v12.8h - MOV v13.d[0], v12.d[1] + rev64 v10.8h, v10.8h + MOV v11.d[0], v10.d[1] + rev64 v12.8h, v12.8h + MOV v13.d[0], v12.d[1] - uMULL v30.4s, v0.4h, v9.4h - uMULL v28.4s, v2.4h, v8.4h - uMULL v26.4s, v0.4h, v8.4h - uMULL v24.4s, v2.4h, v9.4h + uMULL v30.4s, v0.4h, v9.4h + uMULL v28.4s, v2.4h, v8.4h + uMULL v26.4s, v0.4h, v8.4h + uMULL v24.4s, v2.4h, v9.4h - ushR v30.4s, v30.4s, #16 - ushR v28.4s, v28.4s, #16 + ushR v30.4s, v30.4s,#16 + ushR v28.4s, v28.4s,#16 - sMLAL v30.4s, v1.4h, v9.4h - sMLAL v28.4s, v3.4h, v8.4h + sMLAL v30.4s, v1.4h, v9.4h + sMLAL v28.4s, v3.4h, v8.4h - ushR v26.4s, v26.4s, #16 - ushR v24.4s, v24.4s, #16 + ushR v26.4s, v26.4s,#16 + ushR v24.4s, v24.4s,#16 - sMLAL v26.4s, v1.4h, v8.4h - sMLAL v24.4s, v3.4h, v9.4h + sMLAL v26.4s, v1.4h, v8.4h + sMLAL v24.4s, v3.4h, v9.4h - ADD v30.4s, v30.4s , v28.4s - NEG v30.4s, v30.4s + ADD v30.4s, v30.4s , v28.4s + NEG v30.4s, v30.4s - uMULL v22.4s, v4.4h, v8.4h + uMULL v22.4s, v4.4h, v8.4h - SUB v28.4s, v24.4s , v26.4s + SUB v28.4s, v24.4s , v26.4s - mov v26.16b, v30.16b - mov v24.16b, v28.16b + mov v26.16b, v30.16b + mov v24.16b, v28.16b // VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] //VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] - uMULL v2.4s, v24.4h, v18.4h - uMULL v0.4s, v26.4h, v18.4h + uMULL v2.4s, v24.4h, v18.4h + uMULL v0.4s, v26.4h, v18.4h - ushR v22.4s, v22.4s, #16 - sMLAL v22.4s, v5.4h, v8.4h + ushR v22.4s, v22.4s,#16 + sMLAL v22.4s, v5.4h, v8.4h - ushR v2.4s, v2.4s, #16 - ushR v0.4s, v0.4s, #16 - sMLAL v2.4s, v25.4h, v18.4h - sMLAL v0.4s, v27.4h, v18.4h + ushR v2.4s, v2.4s,#16 + ushR v0.4s, v0.4s,#16 + sMLAL v2.4s, v25.4h, v18.4h + sMLAL v0.4s, v27.4h, v18.4h - uMULL v24.4s, v4.4h, v9.4h - uMULL v26.4s, v6.4h, v8.4h + uMULL v24.4s, v4.4h, v9.4h + uMULL v26.4s, v6.4h, v8.4h - NEG v2.4s, v2.4s - ADD v28.4s, v28.4s , v0.4s - ADD v30.4s, v30.4s , v2.4s + NEG v2.4s, v2.4s + ADD v28.4s, v28.4s , v0.4s + ADD v30.4s, v30.4s , v2.4s - uMULL v0.4s, v6.4h, v9.4h - sshR v24.4s, v24.4s, #16 - sMLAL v24.4s, v5.4h, v9.4h - sshR v26.4s, v26.4s, #16 - sshR v0.4s, v0.4s, #16 - sMLAL v26.4s, v7.4h, v8.4h - sMLAL v0.4s, v7.4h, v9.4h + uMULL v0.4s, v6.4h, v9.4h + sshR v24.4s, v24.4s,#16 + sMLAL v24.4s, v5.4h, v9.4h + sshR v26.4s, v26.4s,#16 + sshR v0.4s, v0.4s,#16 + sMLAL v26.4s, v7.4h, v8.4h + sMLAL v0.4s, v7.4h, v9.4h - ADD v22.4s, v22.4s , v0.4s - NEG v22.4s, v22.4s - SUB v24.4s, v26.4s , v24.4s + ADD v22.4s, v22.4s , v0.4s + NEG v22.4s, v22.4s + SUB v24.4s, v26.4s , v24.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v14.4s, w11 - SQADD v28.4s, v28.4s , v14.4s + //sxtw x11,w11 + MOV w11, w26 + dup v14.4s,w11 + SQADD v28.4s, v28.4s , v14.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v0.4s, w11 - sQshL v28.4s, v28.4s, v0.4s + //sxtw x11,w11 + MOV w11, w25 + dup v0.4s,w11 + sQshL v28.4s, v28.4s, v0.4s - mov v0.16b, v22.16b - mov v14.16b, v24.16b + mov v0.16b, v22.16b + mov v14.16b, v24.16b // VUZP.16 D22, D23 - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] + UZP1 v19.8h, v22.8h, v22.8h + UZP2 v21.8h, v22.8h, v22.8h + MOV v22.d[0], v19.d[0] + MOV v23.d[0], v21.d[0] -// VUZP.16 D24, D25 + // VUZP.16 D24, D25 - UZP1 v19.8h, v24.8h, v24.8h - UZP2 v21.8h, v24.8h, v24.8h - MOV v24.d[0], v19.d[0] - MOV v25.d[0], v21.d[0] + UZP1 v19.8h, v24.8h, v24.8h + UZP2 v21.8h, v24.8h, v24.8h + MOV v24.d[0], v19.d[0] + MOV v25.d[0], v21.d[0] - uMULL v8.4s, v24.4h, v18.4h - uMULL v26.4s, v22.4h, v18.4h + uMULL v8.4s, v24.4h, v18.4h + uMULL v26.4s, v22.4h, v18.4h - NEG v2.4s, v30.4s + NEG v2.4s, v30.4s // VUZP.16 D30, D31 - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] + UZP1 v19.8h, v30.8h, v30.8h + UZP2 v21.8h, v30.8h, v30.8h + MOV v30.d[0], v19.d[0] + MOV v30.d[1], v21.d[0] // VUZP.16 D2, D3 - UZP1 v19.8h, v2.8h, v2.8h - UZP2 v21.8h, v2.8h, v2.8h - MOV v2.d[0], v19.d[0] - MOV v3.d[0], v21.d[0] + UZP1 v19.8h, v2.8h, v2.8h + UZP2 v21.8h, v2.8h, v2.8h + MOV v2.d[0], v19.d[0] + MOV v3.d[0], v21.d[0] - uMULL v4.4s, v30.4h, v12.4h - uMULL v6.4s, v2.4h, v13.4h + uMULL v4.4s, v30.4h, v12.4h + uMULL v6.4s, v2.4h, v13.4h - ushR v8.4s, v8.4s, #16 - ushR v26.4s, v26.4s, #16 + ushR v8.4s, v8.4s,#16 + ushR v26.4s, v26.4s,#16 - sMLAL v8.4s, v25.4h, v18.4h - sMLAL v26.4s, v23.4h, v18.4h + sMLAL v8.4s, v25.4h, v18.4h + sMLAL v26.4s, v23.4h, v18.4h - ushR v4.4s, v4.4s, #16 - ushR v6.4s, v6.4s, #16 + ushR v4.4s, v4.4s,#16 + ushR v6.4s, v6.4s,#16 - MOV v19.d[0], v30.d[1] + MOV v19.d[0], v30.d[1] - sMLAL v4.4s, v19.4h, v12.4h - sMLAL v6.4s, v3.4h, v13.4h + sMLAL v4.4s, v19.4h, v12.4h + sMLAL v6.4s, v3.4h, v13.4h - NEG v8.4s, v8.4s - ADD v14.4s, v14.4s , v26.4s - ADD v0.4s, v0.4s , v8.4s + NEG v8.4s, v8.4s + ADD v14.4s, v14.4s , v26.4s + ADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #120] - //sxtw x11,w11 - MOV w11, w26 - dup v8.4s, w11 - SQADD v0.4s, v0.4s , v8.4s + //sxtw x11,w11 + MOV w11, w26 + dup v8.4s,w11 + SQADD v0.4s, v0.4s , v8.4s //LDR w11, [sp, #116] - //sxtw x11,w11 - MOV w11, w25 - dup v26.4s, w11 - sQshL v0.4s, v0.4s, v26.4s + //sxtw x11,w11 + MOV w11, w25 + dup v26.4s,w11 + sQshL v0.4s, v0.4s, v26.4s - mov v26.16b, v28.16b + mov v26.16b, v28.16b MOV x6, x4 - LD1 {v28.2s, v29.2s}, [x4], #16 - movi v19.2s, #0x00000000 - LD1 {v30.s}[0], [x4], #4 - LD1 {v30.s}[1], [x4], #4 - LD1 {v19.s}[0], [x4], #4 + LD1 {v28.2s, v29.2s}, [x4],#16 + movi v19.2s, #0x00000000 + LD1 {v30.s}[0],[x4],#4 + LD1 {v30.s}[1],[x4],#4 + LD1 {v19.s}[0],[x4],#4 - MOV v28.d[1], v29.d[0] - MOV v30.d[1], v19.d[0] + MOV v28.d[1], v29.d[0] + MOV v30.d[1], v19.d[0] //VUZP.32 Q14, Q15 - UZP1 v19.4s, v28.4s, v30.4s - UZP2 v30.4s, v28.4s, v30.4s - MOV v28.16b, v19.16b - MOV v29.d[0], v28.d[1] + UZP1 v19.4s, v28.4s, v30.4s + UZP2 v30.4s, v28.4s, v30.4s + MOV v28.16b, v19.16b + MOV v29.d[0], v28.d[1] - ST1 {v26.s}[0], [x6], #4 - ST1 {v0.s}[0], [x6], #4 - ST1 {v26.s}[1], [x6], #4 - ST1 {v0.s}[1], [x6], #4 - ST1 {v26.s}[2], [x6], #4 - ST1 {v0.s}[2], [x6], #4 - ST1 {v26.s}[3], [x6], #4 + ST1 {v26.s}[0],[x6],#4 + ST1 {v0.s}[0],[x6],#4 + ST1 {v26.s}[1],[x6],#4 + ST1 {v0.s}[1],[x6],#4 + ST1 {v26.s}[2],[x6],#4 + ST1 {v0.s}[2],[x6],#4 + ST1 {v26.s}[3],[x6],#4 - movi v1.2s, #0 + movi v1.2s, #0 //VADDL.S16 Q0, D13, D1 - SADDL v0.4s, v13.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v13.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v26.2d, v28.2s, v0.2s - Sqxtn v8.2s, v26.2d - sMULL v26.2d, v29.2s, v1.2s - Sqxtn v9.2s, v26.2d - MOV v8.d[1], v9.d[0] - movi v1.2s, #0 + sMULL v26.2d, v28.2s, v0.2s + Sqxtn v8.2s, v26.2d + sMULL v26.2d, v29.2s, v1.2s + Sqxtn v9.2s, v26.2d + MOV v8.d[1], v9.d[0] + movi v1.2s, #0 //VADDL.S16 Q0, D12, D1 - SADDL v0.4s, v12.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v12.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v24.2d, v28.2s, v0.2s - Sqxtn v26.2s, v24.2d - sMULL v24.2d, v29.2s, v1.2s - Sqxtn v27.2s, v24.2d - MOV v26.d[1], v27.d[0] + sMULL v24.2d, v28.2s, v0.2s + Sqxtn v26.2s, v24.2d + sMULL v24.2d, v29.2s, v1.2s + Sqxtn v27.2s, v24.2d + MOV v26.d[1], v27.d[0] - sQshL v4.4s, v4.4s, v16.4s - sQshL v6.4s, v6.4s, v16.4s + sQshL v4.4s, v4.4s, v16.4s + sQshL v6.4s, v6.4s, v16.4s - SQSUB v4.4s, v4.4s , v8.4s - SQSUB v6.4s, v6.4s , v26.4s + SQSUB v4.4s, v4.4s , v8.4s + SQSUB v6.4s, v6.4s , v26.4s - NEG v26.4s, v14.4s + NEG v26.4s, v14.4s //VUZP.16 D14, D15 - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] + UZP1 v19.8h, v14.8h, v14.8h + UZP2 v21.8h, v14.8h, v14.8h + MOV v14.d[0], v19.d[0] + MOV v15.d[0], v21.d[0] -// VUZP.16 D26, D27 +// VUZP.16 D26, D27 - UZP1 v19.8h, v26.8h, v26.8h - UZP2 v21.8h, v26.8h, v26.8h - MOV v26.d[0], v19.d[0] - MOV v27.d[0], v21.d[0] + UZP1 v19.8h, v26.8h, v26.8h + UZP2 v21.8h, v26.8h, v26.8h + MOV v26.d[0], v19.d[0] + MOV v27.d[0], v21.d[0] - movi v1.2s, #0 + movi v1.2s, #0 //VADDL.S16 Q0, D10, D1 - SADDL v0.4s, v10.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v10.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v22.2d, v30.2s, v0.2s - Sqxtn v24.2s, v22.2d - sMULL2 v22.2d, v30.4s, v0.4s - Sqxtn v25.2s, v22.2d - MOV v24.d[1], v25.d[0] + sMULL v22.2d, v30.2s, v0.2s + Sqxtn v24.2s, v22.2d + sMULL2 v22.2d, v30.4s, v0.4s + Sqxtn v25.2s, v22.2d + MOV v24.d[1], v25.d[0] - movi v1.2s, #0 + movi v1.2s, #0 // VADDL.S16 Q0, D11, D1 - SADDL v0.4s, v11.4h, v1.4h - MOV v1.d[0], v0.d[1] + SADDL v0.4s, v11.4h, v1.4h + MOV v1.d[0], v0.d[1] - sMULL v8.2d, v30.2s, v0.2s - Sqxtn v22.2s, v8.2d - sMULL2 v8.2d, v30.4s, v0.4s - Sqxtn v23.2s, v8.2d - MOV v22.d[1], v23.d[0] + sMULL v8.2d, v30.2s, v0.2s + Sqxtn v22.2s, v8.2d + sMULL2 v8.2d, v30.4s, v0.4s + Sqxtn v23.2s, v8.2d + MOV v22.d[1], v23.d[0] - uMULL v8.4s, v26.4h, v11.4h - uMULL v30.4s, v14.4h, v10.4h + uMULL v8.4s, v26.4h, v11.4h + uMULL v30.4s, v14.4h, v10.4h - ushR v8.4s, v8.4s, #16 + ushR v8.4s, v8.4s,#16 - ushR v30.4s, v30.4s, #16 + ushR v30.4s, v30.4s,#16 - sMLAL v8.4s, v27.4h, v11.4h + sMLAL v8.4s, v27.4h, v11.4h - sMLAL v30.4s, v15.4h, v10.4h + sMLAL v30.4s, v15.4h, v10.4h - sQshL v4.4s, v4.4s, #2 + MOV V14.16B , V4.16B - sQshL v6.4s, v6.4s, #2 + //mov v15.8b, v6.8b + sQshL v8.4s, v8.4s, v16.4s - SQADD v14.4s, v4.4s , v20.4s + sQshL v30.4s, v30.4s, v16.4s - SQADD v6.4s, v6.4s , v20.4s + SQSUB v8.4s, v8.4s , v24.4s - sshR v14.4s, v14.4s, #16 + SQSUB v22.4s, v30.4s , v22.4s -// VUZP.16 D14, D15 - - UZP1 v19.8h, v14.8h, v14.8h - UZP2 v21.8h, v14.8h, v14.8h - MOV v14.d[0], v19.d[0] - MOV v15.d[0], v21.d[0] - - sshR v6.4s, v6.4s, #16 - - //VUZP.16 D6, D7 - - UZP1 v19.8h, v6.8h, v6.8h - UZP2 v21.8h, v6.8h, v6.8h - MOV v6.d[0], v19.d[0] - MOV v7.d[0], v21.d[0] - - mov v15.8b, v6.8b - sQshL v8.4s, v8.4s, v16.4s - - sQshL v30.4s, v30.4s, v16.4s - - SQSUB v8.4s, v8.4s , v24.4s - - SQSUB v22.4s, v30.4s , v22.4s - - sQshL v30.4s, v8.4s, #2 - - sQshL v22.4s, v22.4s, #2 - - SQADD v30.4s, v30.4s , v20.4s - SQADD v22.4s, v22.4s , v20.4s - - sshR v30.4s, v30.4s, #16 - -// VUZP.16 D30, D31 - - UZP1 v19.8h, v30.8h, v30.8h - UZP2 v21.8h, v30.8h, v30.8h - MOV v30.d[0], v19.d[0] - MOV v30.d[1], v21.d[0] - - sshR v22.4s, v22.4s, #16 - -// VUZP.16 D22, D23 - - UZP1 v19.8h, v22.8h, v22.8h - UZP2 v21.8h, v22.8h, v22.8h - MOV v22.d[0], v19.d[0] - MOV v23.d[0], v21.d[0] - - mov v23.8b, v30.8b + MOV V30.16B, V8.16B - ST1 {v14.h}[0], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[0], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[1], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[1], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[2], [x0] - ADD x0, x0, x9 - ST1 {v22.h}[2], [x0] - ADD x0, x0, x9 - ST1 {v14.h}[3], [x0] - ADD x0, x0, x9 - ST1 {v15.h}[0], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[0], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[1], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[1], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[2], [x5] - ADD x5, x5, x10 - ST1 {v23.h}[2], [x5] - ADD x5, x5, x10 - ST1 {v15.h}[3], [x5] - ADD x5, x5, x10 - // VPOP {d8 - d15} - // LDMFD sp!, {x4-x12} - //ldp x19, x20,[sp],#16 - pop_v_regs - ret - //BX x14 + + ST1 {V14.S}[0],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[0],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[1],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[1],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[2],[x0] + ADD x0, x0, x9 + ST1 {V22.S}[2],[x0] + ADD x0, x0, x9 + ST1 {V14.S}[3],[x0] + ADD x0, x0, x9 + + ST1 {V6.S}[0],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[0],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[1],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[1],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[2],[x5] + ADD x5, x5, x10 + ST1 {V30.S}[2],[x5] + ADD x5, x5, x10 + ST1 {V6.S}[3],[x5] + ADD x5, x5, x10 + + pop_v_regs + ret + + diff --git a/decoder/ixheaacd_aac_imdct.c b/decoder/ixheaacd_aac_imdct.c index 43f2025..6b158de 100644 --- a/decoder/ixheaacd_aac_imdct.c +++ b/decoder/ixheaacd_aac_imdct.c @@ -467,14 +467,14 @@ VOID ixheaacd_post_twiddle_dec(WORD32 out_ptr[], WORD32 spec_data[], } VOID ixheaacd_post_twid_overlap_add_dec( - WORD16 pcm_out[], WORD32 spec_data[], + WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) { WORD i; WORD16 cos, cos1, sin, sin1; WORD32 size = npoints / 2; - WORD16 *pcmout1 = pcm_out + (ch_fac * size); + WORD32 *pcmout1 = pcm_out + (ch_fac * size); const WORD16 *cos_sin_ptr = ptr_imdct_tables->cosine_array_2048_256; pcm_out = pcmout1 - ch_fac; @@ -511,7 +511,7 @@ VOID ixheaacd_post_twid_overlap_add_dec( ixheaacd_shl32_sat(ixheaacd_mult32x16lin32(outi, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( @@ -520,7 +520,7 @@ VOID ixheaacd_post_twid_overlap_add_dec( q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1))); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcmout1 = accu; pcmout1 += ch_fac; @@ -550,14 +550,16 @@ VOID ixheaacd_post_twid_overlap_add_dec( accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat(ixheaacd_mult32x16lin32(outr, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outr), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)win1)); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcmout1 = accu; pcmout1 += ch_fac; tempr = *(spec_data - i); @@ -585,14 +587,15 @@ VOID ixheaacd_post_twid_overlap_add_dec( accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat(ixheaacd_mult32x16lin32(outi, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outi), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1))); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcmout1 = accu; pcmout1 += ch_fac; } cos1 = *cos_sin_ptr++; @@ -620,14 +623,16 @@ VOID ixheaacd_post_twid_overlap_add_dec( accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat(ixheaacd_mult32x16lin32(outr, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( ixheaacd_shl32_sat( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outr), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)win1)); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcmout1 = accu; pcmout1 += ch_fac; } else { q_shift = -q_shift; @@ -663,7 +668,7 @@ VOID ixheaacd_post_twid_overlap_add_dec( ixheaacd_shr32(ixheaacd_mult32x16lin32(outi, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( @@ -672,7 +677,7 @@ VOID ixheaacd_post_twid_overlap_add_dec( q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1))); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcmout1 = accu; pcmout1 += ch_fac; for (i = size - 2; i != 0;) { @@ -701,14 +706,16 @@ VOID ixheaacd_post_twid_overlap_add_dec( ixheaacd_shr32(ixheaacd_mult32x16lin32(outr, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcm_out = accu; pcm_out -= ch_fac; + accu = ixheaacd_sub32_sat( ixheaacd_shr32( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outr), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)win1)); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + + *pcmout1 = accu; pcmout1 += ch_fac; tempr = *(spec_data - i); @@ -735,15 +742,16 @@ VOID ixheaacd_post_twid_overlap_add_dec( ixheaacd_shr32(ixheaacd_mult32x16lin32(outi, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcm_out = accu; pcm_out -= ch_fac; + accu = ixheaacd_sub32_sat( ixheaacd_shr32( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outi), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1))); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcmout1 = accu; pcmout1 += ch_fac; } cos1 = *cos_sin_ptr++; @@ -773,14 +781,14 @@ VOID ixheaacd_post_twid_overlap_add_dec( ixheaacd_shr32(ixheaacd_mult32x16lin32(outr, win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)(win1 >> 16))); - *pcm_out = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcm_out = accu; pcm_out -= ch_fac; accu = ixheaacd_sub32_sat( ixheaacd_shr32( ixheaacd_mult32x16hin32_drc(ixheaacd_negate32(outr), win1), q_shift), ixheaacd_mult32x16lin32_drc(overlap_data, (WORD16)win1)); - *pcmout1 = ixheaacd_round16(ixheaacd_shl32_sat(accu, 2)); + *pcmout1 = accu; pcmout1 += ch_fac; } } diff --git a/decoder/ixheaacd_aac_imdct.h b/decoder/ixheaacd_aac_imdct.h index d6dc58f..950eef9 100644 --- a/decoder/ixheaacd_aac_imdct.h +++ b/decoder/ixheaacd_aac_imdct.h @@ -38,19 +38,19 @@ VOID ixheaacd_post_twiddle_armv8( ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD32 npoints); VOID ixheaacd_post_twid_overlap_add_dec( - WORD16 pcm_out[], WORD32 spec_data[], + WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac); VOID ixheaacd_post_twid_overlap_add_armv7( - WORD16 pcm_out[], WORD32 spec_data[], + WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac); VOID ixheaacd_post_twid_overlap_add_armv8( - WORD16 pcm_out[], WORD32 spec_data[], + WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac); diff --git a/decoder/ixheaacd_aacdecoder.c b/decoder/ixheaacd_aacdecoder.c index 6c26d2d..c9c1547 100644 --- a/decoder/ixheaacd_aacdecoder.c +++ b/decoder/ixheaacd_aacdecoder.c @@ -85,16 +85,18 @@ #define EXT_FILL_DATA 1 #define EXT_FIL 0 +#define MIN(x, y) ((x) > (y) ? (y) : (x)) + WORD32 ixheaacd_aacdec_decodeframe( ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec, - ia_aac_dec_scratch_struct *aac_scratch_ptrs, WORD16 *time_data, + ia_aac_dec_scratch_struct *aac_scratch_ptrs, VOID *time_data_tmp, FLAG frame_status, WORD *type, WORD *ch_idx, WORD init_flag, WORD channel, WORD *element_index_order, WORD skip_full_decode, WORD ch_fac, WORD slot_element, WORD max_channels, WORD32 total_channels, WORD32 frame_length, WORD32 frame_size, ia_drc_dec_struct *pstr_drc_dec, WORD32 object_type, WORD32 ch_config, ia_eld_specific_config_struct eld_specific_config, WORD16 adtsheader, - ia_drc_dec_struct *drc_dummy) + ia_drc_dec_struct *drc_dummy, UWORD8 *slot_pos) { WORD ch, ele_type; @@ -129,6 +131,8 @@ WORD32 ixheaacd_aacdec_decodeframe( WORD32 *work_buffer_2 = aac_scratch_ptrs->extra_scr_4k[2]; p_state_enhaacplus_dec = p_obj_exhaacplus_dec->p_state_aac; + WORD32 *time_data = (WORD32 *)time_data_tmp; + aac_dec_handle = p_state_enhaacplus_dec->pstr_aac_dec_info[*ch_idx]; it_bit_buff = p_state_enhaacplus_dec->ptr_bit_stream; @@ -810,8 +814,14 @@ WORD32 ixheaacd_aacdec_decodeframe( if (skip_full_decode == 0) { ixheaacd_imdct_process( aac_dec_handle->pstr_aac_dec_overlap_info[ch], spec_coef[ch], - &str_ics_info[ch], time_data + slot_element, (WORD16)ch_fac, - scratch[ch], aac_dec_handle->pstr_aac_tables, object_type); + &str_ics_info[ch], time_data + slot_element, ch_fac, scratch[ch], + aac_dec_handle->pstr_aac_tables, object_type, slot_element); + + if (slot_pos != NULL) *slot_pos = slot_element; + + p_obj_exhaacplus_dec->p_state_aac + ->qshift_adj[p_obj_exhaacplus_dec->p_state_aac->qshift_cnt++] = + str_ics_info[ch].qshift_adj; aac_dec_handle->ptr_aac_dec_static_channel_info[ch] ->overlap_add_data.win_shape = str_ics_info[ch].window_shape; @@ -827,7 +837,7 @@ WORD32 ixheaacd_aacdec_decodeframe( time_data + slot_element, overlap1, aac_dec_handle->samples_per_frame, object_type, (WORD16)ch_fac, str_ics_info[ch].window_sequence, - (WORD16 *)ptr_long_window_next); + (WORD16 *)ptr_long_window_next, slot_element); } else { ixheaacd_lt_update_state( aac_dec_handle->ptr_aac_dec_static_channel_info[ch] @@ -835,7 +845,7 @@ WORD32 ixheaacd_aacdec_decodeframe( time_data + slot_element, overlap1, aac_dec_handle->samples_per_frame, object_type, (WORD16)ch_fac, str_ics_info[ch].window_sequence, - (WORD16 *)ptr_short_window_next); + (WORD16 *)ptr_short_window_next, slot_element); } } } diff --git a/decoder/ixheaacd_api.c b/decoder/ixheaacd_api.c index f26901c..8e9a2a6 100644 --- a/decoder/ixheaacd_api.c +++ b/decoder/ixheaacd_api.c @@ -119,6 +119,18 @@ #define IXHEAACD_CCE_DEC_INFO_MEM_SIZE (610) #define IXHEAACD_CCE_DEC_INFO_MEM_SIZE_8 (IXHEAACD_CCE_DEC_INFO_MEM_SIZE + 8) +#define LD_OBJ -2 + +#define MIN(x, y) ((x) > (y) ? (y) : (x)) + +WORD32 ixheaacd_peak_limiter_init(ia_peak_limiter_struct *peak_limiter, + UWORD32 num_channels, UWORD32 sample_rate, + FLOAT32 *buffer, UWORD32 *delay_in_samples); + +VOID ixheaacd_peak_limiter_process(ia_peak_limiter_struct *peak_limiter, + VOID *samples, UWORD32 frame_len, + WORD8 *qshift_adj); + IA_ERRORCODE ixheaacd_dec_mem_api( ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec, WORD32 i_cmd, WORD32 i_idx, VOID *pv_value) { @@ -277,11 +289,41 @@ static VOID ixheaacd_allocate_aac_scr( VOID ixheaacd_allocate_sbr_scr(ia_sbr_scr_struct *sbr_scratch_struct, VOID *base_scratch_ptr, VOID *output_ptr, WORD total_elements, WORD ch_fac, - WORD32 audio_object_type) { + WORD32 audio_object_type, WORD32 total_channels, + WORD8 *p_qshift_arr, UWORD8 slot_pos, + UWORD8 num_ch) { WORD32 temp = 0; + WORD32 j, i; sbr_scratch_struct->ptr_work_buf_core = base_scratch_ptr; sbr_scratch_struct->ptr_work_buf = (WORD8 *)base_scratch_ptr + (18 * 1024); + if (p_qshift_arr != NULL && *p_qshift_arr != LD_OBJ) { + WORD32 *tmp_buf = (WORD32 *)output_ptr; + + for (j = 1; j < num_ch; j++) { + if ((*p_qshift_arr + j) == 0) + *(p_qshift_arr + j) = *(p_qshift_arr + j - 1); + } + + if (total_channels > 2) { + for (j = 0; j < num_ch; j++) { + for (i = 0; i < 1024; i++) { + *((WORD16 *)tmp_buf + slot_pos + total_channels * i + j) = + ixheaacd_round16(ixheaacd_shl32_sat( + *(tmp_buf + slot_pos + total_channels * i + j), + *(p_qshift_arr + j))); + } + } + } else { + for (j = 0; j < num_ch; j++) { + for (i = 0; i < 1024; i++) { + *((WORD16 *)tmp_buf + total_channels * i + j) = + ixheaacd_round16(ixheaacd_shl32_sat( + *(tmp_buf + total_channels * i + j), *(p_qshift_arr + j))); + } + } + } + } if (total_elements > 1) { sbr_scratch_struct->extra_scr_1k[0] = (WORD8 *)base_scratch_ptr + (18 * 1024); @@ -851,6 +893,9 @@ IA_ERRORCODE ixheaacd_dec_api(pVOID p_ia_enhaacplus_dec_obj, WORD32 i_cmd, p_obj_exhaacplus_dec->p_state_aac->fatal_err_present) { err_code = IA_FATAL_ERROR; } else { + memset(p_obj_exhaacplus_dec->p_state_aac->qshift_adj, 0, + sizeof(p_obj_exhaacplus_dec->p_state_aac->qshift_adj)); + p_obj_exhaacplus_dec->p_state_aac->qshift_cnt = 0; err_code = ixheaacd_dec_execute(p_obj_exhaacplus_dec); } if (err_code != IA_NO_ERROR) { @@ -1025,6 +1070,7 @@ IA_ERRORCODE ixheaacd_decoder_flush_api( p_obj_exhaacplus_dec->aac_config.ui_coupling_channel = 0; p_obj_exhaacplus_dec->aac_config.downmix = 0; + p_obj_exhaacplus_dec->p_state_aac->peak_lim_init = 0; { ia_aac_dec_tables_struct *pstr_aac_tables = @@ -1817,7 +1863,8 @@ IA_ERRORCODE ixheaacd_dec_init( p_state_enhaacplus_dec->ch_config, p_state_enhaacplus_dec->eld_specific_config, p_state_enhaacplus_dec->s_adts_hdr_present, - &p_state_enhaacplus_dec->drc_dummy); + &p_state_enhaacplus_dec->drc_dummy, + &p_state_enhaacplus_dec->slot_pos); if (p_state_enhaacplus_dec->pstr_drc_dec->drc_element_found == 1) { if (p_obj_exhaacplus_dec->aac_config.i_loud_ref_level < 0) { @@ -1918,7 +1965,8 @@ IA_ERRORCODE ixheaacd_dec_init( WORD16 num_channels_1_t = num_channels_1; ixheaacd_allocate_sbr_scr( &sbr_scratch_struct, p_state_enhaacplus_dec->aac_scratch_mem_v, - time_data, 1, 1, p_state_enhaacplus_dec->audio_object_type); + time_data, 1, 1, p_state_enhaacplus_dec->audio_object_type, 0, NULL, + 0, 0); if (ixheaacd_applysbr( p_state_enhaacplus_dec->str_sbr_dec_info[ch_idx], @@ -2246,7 +2294,7 @@ IA_ERRORCODE ixheaacd_dec_execute( WORD type; WORD total_channels = 0; WORD total_elements = 0; - WORD16 *actual_out_buffer; + WORD16 *actual_out_buffer = NULL; WORD ps_enable; WORD esbr_mono_downmix = 0; WORD8 element_used[MAX_BS_ELEMENT]; @@ -2366,7 +2414,7 @@ IA_ERRORCODE ixheaacd_dec_execute( scratch_pointer = 12 * 1024; p_state_enhaacplus_dec->coup_ch_output = - (WORD16 *)((WORD8 *) + (WORD32 *)((WORD8 *) p_obj_exhaacplus_dec->p_state_aac->aac_scratch_mem_v + scratch_pointer); } @@ -2382,6 +2430,52 @@ IA_ERRORCODE ixheaacd_dec_execute( p_obj_exhaacplus_dec->p_state_aac->ui_out_bytes = 0; if (p_state_enhaacplus_dec->ui_in_bytes == 0) { + WORD32 i, j; + if (p_state_enhaacplus_dec->peak_lim_init == 1) { + p_obj_exhaacplus_dec->p_state_aac->ui_out_bytes = + (p_state_enhaacplus_dec->peak_limiter.attack_time_samples) * + total_channels * sizeof(WORD16); + + for (j = 0; j < total_channels; j++) { + for (i = 0; + i < (p_state_enhaacplus_dec->peak_limiter.attack_time_samples - + p_state_enhaacplus_dec->peak_limiter.delayed_input_index); + i++) { + *(time_data + total_channels * i + j) = ixheaacd_round16( + *(p_state_enhaacplus_dec->peak_limiter.delayed_input + + (p_state_enhaacplus_dec->peak_limiter.delayed_input_index) * + total_channels + + total_channels * i + j)); + } + } + + for (j = 0; j < total_channels; j++) { + for (i = 0; + i < p_state_enhaacplus_dec->peak_limiter.delayed_input_index; + i++) { + *(time_data + + (p_state_enhaacplus_dec->peak_limiter.attack_time_samples - + p_state_enhaacplus_dec->peak_limiter.delayed_input_index) * + total_channels + + total_channels * i + j) = + ixheaacd_round16( + *(p_state_enhaacplus_dec->peak_limiter.delayed_input + + total_channels * i + j)); + } + } + + if (p_obj_exhaacplus_dec->aac_config.dup_stereo_flag) { + for (i = 0; + i < (p_state_enhaacplus_dec->peak_limiter.attack_time_samples); + i++) { + time_data[2 * i + 1] = time_data[2 * i + 0]; + } + } + p_state_enhaacplus_dec->peak_lim_init = 0xFF; + } else { + p_obj_exhaacplus_dec->p_state_aac->ui_out_bytes = 0; + } + p_state_enhaacplus_dec->i_bytes_consumed = 0; return IA_NO_ERROR; } @@ -2524,6 +2618,10 @@ IA_ERRORCODE ixheaacd_dec_execute( p_state_enhaacplus_dec->pstr_drc_dec->state = 1; } + WORD16 *intermediate_scr = + (WORD16 *)(WORD8 *)p_state_enhaacplus_dec->aac_scratch_mem_v + + (128 * 1024); + for (ch_idx1 = 0; ch_idx1 < total_elements; ch_idx1++) { WORD32 skip_full_decode = 0; WORD32 ch_idx = ch_idx1; @@ -2601,7 +2699,8 @@ IA_ERRORCODE ixheaacd_dec_execute( if (p_obj_exhaacplus_dec->aac_config.element_type[1] < 3 && p_obj_exhaacplus_dec->aac_config.element_type[1] > 0 && p_obj_exhaacplus_dec->aac_config.ui_max_channels > 2) { - actual_out_buffer = p_state_enhaacplus_dec->coup_ch_output; + actual_out_buffer = + (WORD16 *)(VOID *)p_state_enhaacplus_dec->coup_ch_output; } ch_fac = 1; slot_ele = 0; @@ -2633,7 +2732,21 @@ IA_ERRORCODE ixheaacd_dec_execute( p_state_enhaacplus_dec->ch_config, p_state_enhaacplus_dec->eld_specific_config, p_state_enhaacplus_dec->s_adts_hdr_present, - &p_state_enhaacplus_dec->drc_dummy); + &p_state_enhaacplus_dec->drc_dummy, + &p_state_enhaacplus_dec->slot_pos); + + p_state_enhaacplus_dec->slot_pos -= (channel - 1); + p_state_enhaacplus_dec->sbr_present = 0; + + if (p_obj_exhaacplus_dec->p_state_aac->qshift_adj[0] != LD_OBJ && + p_state_enhaacplus_dec->frame_counter == 0) { + ixheaacd_peak_limiter_init( + &p_state_enhaacplus_dec->peak_limiter, total_channels, + p_obj_exhaacplus_dec->p_state_aac->p_config->ui_samp_freq, + &p_state_enhaacplus_dec->peak_limiter.buffer[0], + &p_obj_exhaacplus_dec->p_state_aac->delay_in_samples); + p_obj_exhaacplus_dec->p_state_aac->peak_lim_init = 1; + } if (p_state_enhaacplus_dec->audio_object_type < ER_OBJECT_START || (p_state_enhaacplus_dec->audio_object_type != AOT_ER_AAC_LD && @@ -2711,10 +2824,15 @@ IA_ERRORCODE ixheaacd_dec_execute( if (p_state_enhaacplus_dec->str_sbr_dec_info[ch_idx] && p_state_enhaacplus_dec->pstr_stream_sbr[0][0].no_elements) { ia_sbr_scr_struct sbr_scratch_struct; - ixheaacd_allocate_sbr_scr(&sbr_scratch_struct, - p_state_enhaacplus_dec->aac_scratch_mem_v, - time_data, total_elements, ch_fac, - p_state_enhaacplus_dec->audio_object_type); + ixheaacd_allocate_sbr_scr( + &sbr_scratch_struct, p_state_enhaacplus_dec->aac_scratch_mem_v, + time_data, total_elements, ch_fac, + p_state_enhaacplus_dec->audio_object_type, total_channels, + p_obj_exhaacplus_dec->p_state_aac->qshift_adj, + p_state_enhaacplus_dec->slot_pos, channel); + + p_state_enhaacplus_dec->sbr_present = 1; + p_state_enhaacplus_dec->peak_lim_init = 0; if (ixheaacd_applysbr( p_state_enhaacplus_dec->str_sbr_dec_info[ch_idx], @@ -2740,8 +2858,17 @@ IA_ERRORCODE ixheaacd_dec_execute( sample_rate = sample_rate_dec; } + if (p_state_enhaacplus_dec->sbr_present || + p_obj_exhaacplus_dec->p_state_aac->qshift_adj[0] == LD_OBJ) { + num_of_out_samples = frame_size; + + } else { + num_of_out_samples = + frame_size - + MIN(p_obj_exhaacplus_dec->p_state_aac->delay_in_samples, frame_size); + } + p_obj_exhaacplus_dec->aac_config.ui_samp_freq = sample_rate; - num_of_out_samples = frame_size; p_state_enhaacplus_dec->num_channel_last = num_ch; p_state_enhaacplus_dec->num_of_out_samples = num_of_out_samples; @@ -2751,12 +2878,11 @@ IA_ERRORCODE ixheaacd_dec_execute( { if (p_obj_exhaacplus_dec->aac_config.flag_to_stereo == 1 && channel == 1 && total_elements == 1 && num_ch == 1) { - WORD i; num_ch = 2; + p_obj_exhaacplus_dec->aac_config.dup_stereo_flag = 1; - for (i = 0; i < frame_size; i++) { - actual_out_buffer[2 * i + 1] = actual_out_buffer[2 * i + 0]; - } + } else { + p_obj_exhaacplus_dec->aac_config.dup_stereo_flag = 0; } p_obj_exhaacplus_dec->aac_config.ui_n_channels = num_ch; @@ -2769,6 +2895,22 @@ IA_ERRORCODE ixheaacd_dec_execute( else { channel_coupling_flag = 1; } + + if (p_state_enhaacplus_dec->sbr_present && total_channels > 2) { + for (int j = 0; j < channel; j++) { + for (int i = 0; i < frame_size; i++) { + intermediate_scr[total_channels * i + j + + p_state_enhaacplus_dec->slot_pos] = + actual_out_buffer[total_channels * i + j + + p_state_enhaacplus_dec->slot_pos]; + } + } + } + } + + if (p_state_enhaacplus_dec->sbr_present && total_channels > 2) { + memcpy(time_data, intermediate_scr, + sizeof(WORD16) * frame_size * total_channels); } { @@ -2785,12 +2927,63 @@ IA_ERRORCODE ixheaacd_dec_execute( p_state_enhaacplus_dec->frame_counter++; + WORD32 i, j; + if (channel_coupling_flag) { ixheaacd_dec_ind_coupling(p_obj_exhaacplus_dec, p_state_enhaacplus_dec->coup_ch_output, num_of_out_samples, total_channels, time_data); } + for (i = 0; i < total_channels; i++) { + if (p_obj_exhaacplus_dec->p_state_aac->qshift_adj[i + 1] == 0) + p_obj_exhaacplus_dec->p_state_aac->qshift_adj[i + 1] = + p_obj_exhaacplus_dec->p_state_aac->qshift_adj[0]; + } + + if (p_obj_exhaacplus_dec->aac_config.flag_to_stereo == 1 && + total_elements == 1 && num_ch == 2 && + p_obj_exhaacplus_dec->aac_config.dup_stereo_flag == 1) { + WORD i; + + if (!p_state_enhaacplus_dec->sbr_present && + p_obj_exhaacplus_dec->p_state_aac->qshift_adj[0] != LD_OBJ) { + for (i = 0; i < frame_size; i++) { + *((WORD32 *)actual_out_buffer + 2 * i + 1) = + *((WORD32 *)actual_out_buffer + 2 * i); + } + } else { + for (i = 0; i < frame_size; i++) { + *(actual_out_buffer + 2 * i + 1) = *(actual_out_buffer + 2 * i); + } + } + } + + if (!p_state_enhaacplus_dec->sbr_present && + p_obj_exhaacplus_dec->p_state_aac->peak_lim_init == 1 && + p_obj_exhaacplus_dec->p_state_aac->qshift_adj[0] != LD_OBJ) { + ixheaacd_peak_limiter_process( + &p_state_enhaacplus_dec->peak_limiter, time_data, frame_size, + p_obj_exhaacplus_dec->p_state_aac->qshift_adj); + + for (i = 0; i < frame_size * 2; i++) { + for (j = 0; j < total_channels; j++) { + *((WORD16 *)time_data + total_channels * i + j) = + ixheaacd_round16(*((WORD32 *)time_data + total_channels * i + j)); + } + } + + memmove( + time_data, + (time_data + + total_channels * p_obj_exhaacplus_dec->p_state_aac->delay_in_samples), + sizeof(WORD16) * num_of_out_samples * total_channels); + + p_obj_exhaacplus_dec->p_state_aac->delay_in_samples = + p_obj_exhaacplus_dec->p_state_aac->delay_in_samples - + MIN(p_obj_exhaacplus_dec->p_state_aac->delay_in_samples, frame_size); + } + if ((total_channels > 2) && (1 == p_obj_exhaacplus_dec->aac_config.downmix)) { ixheaacd_dec_downmix_to_stereo(p_obj_exhaacplus_dec, num_of_out_samples, total_elements, time_data, total_channels); diff --git a/decoder/ixheaacd_block.c b/decoder/ixheaacd_block.c index 2784edd..0f4afb6 100644 --- a/decoder/ixheaacd_block.c +++ b/decoder/ixheaacd_block.c @@ -1131,9 +1131,11 @@ WORD ixheaacd_huffman_dec_word2(ia_bit_buf_struct *it_bit_buff, WORD32 cb_no, return ret_val; } -void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, WORD16 *out, +void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, VOID *out_tmp, const WORD16 *window, WORD16 q_shift, WORD16 size, - WORD16 stride) { + WORD16 stride , WORD slot_element) { + + WORD32 accu; WORD32 i; WORD16 rounding_fac = -0x2000; @@ -1145,6 +1147,8 @@ void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, WORD16 *out, WORD32 *pwin1, *pwin2; WORD32 *pCoef = &coef[size * 2 - 1 - 0]; + WORD16 * out = (WORD16*)out_tmp - slot_element; + pwin1 = &window_i[size - 1 - 0]; pwin2 = &window_i[size + 0]; @@ -1182,12 +1186,12 @@ void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, WORD16 *out, } } -VOID ixheaacd_over_lap_add1_dec(WORD32 *coef, WORD32 *prev, WORD16 *out, +VOID ixheaacd_over_lap_add1_dec(WORD32 *coef, WORD32 *prev, WORD32 *out, const WORD16 *window, WORD16 q_shift, WORD16 size, WORD16 ch_fac) { WORD32 accu; WORD32 i; - WORD16 rounding_fac = -0x2000; + WORD16 rounding_fac = 0; for (i = 0; i < size; i++) { WORD16 window1, window2; @@ -1198,16 +1202,14 @@ VOID ixheaacd_over_lap_add1_dec(WORD32 *coef, WORD32 *prev, WORD16 *out, ixheaacd_shl32_dir_sat_limit( ixheaacd_mult32x16in32(coef[size * 2 - 1 - i], window2), q_shift), ixheaacd_mac32x16in32_drc(rounding_fac, prev[i], window1)); - out[ch_fac * (size - i - 1)] = - ixheaacd_shr32(ixheaacd_shl32_dir_sat_limit(accu, 2), 16); + out[ch_fac * (size - i - 1)] = accu; accu = ixheaacd_sub32_sat( ixheaacd_shl32_dir_sat_limit( ixheaacd_mult32x16in32(ixheaacd_negate32(coef[size * 2 - 1 - i]), window1), q_shift), ixheaacd_mac32x16in32_drc(rounding_fac, prev[i], window2)); - out[ch_fac * (size + i)] = - ixheaacd_shr32(ixheaacd_shl32_dir_sat_limit(accu, 2), 16); + out[ch_fac * (size + i)] = accu; } } diff --git a/decoder/ixheaacd_block.h b/decoder/ixheaacd_block.h index 739116c..51a1d9f 100644 --- a/decoder/ixheaacd_block.h +++ b/decoder/ixheaacd_block.h @@ -78,15 +78,15 @@ IA_ERRORCODE ixheaacd_read_section_data( WORD32 aac_spect_data_resil_flag, WORD32 aac_sect_data_resil_flag, ia_aac_dec_tables_struct *ptr_aac_tables); -VOID ixheaacd_over_lap_add1_dec(WORD32 *coef, WORD32 *prev, WORD16 *out, +VOID ixheaacd_over_lap_add1_dec(WORD32 *coef, WORD32 *prev, WORD32 *out, const WORD16 *window, WORD16 q_shift, WORD16 size, WORD16 ch_fac); -VOID ixheaacd_over_lap_add1_armv7(WORD32 *coef, WORD32 *prev, WORD16 *out, +VOID ixheaacd_over_lap_add1_armv7(WORD32 *coef, WORD32 *prev, WORD32 *out, const WORD16 *window, WORD16 q_shift, WORD16 size, WORD16 ch_fac); -VOID ixheaacd_over_lap_add1_armv8(WORD32 *coef, WORD32 *prev, WORD16 *out, +VOID ixheaacd_over_lap_add1_armv8(WORD32 *coef, WORD32 *prev, WORD32 *out, const WORD16 *window, WORD16 q_shift, WORD16 size, WORD16 ch_fac); @@ -120,10 +120,10 @@ VOID ixheaacd_spec_to_overlapbuf_armv7(WORD32 *ptr_overlap_buf, WORD32 *ptr_spec_coeff, WORD32 q_shift, WORD32 size); -VOID ixheaacd_overlap_buf_out_dec(WORD16 *out_samples, WORD32 *ptr_overlap_buf, +VOID ixheaacd_overlap_buf_out_dec(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac); -VOID ixheaacd_overlap_buf_out_armv7(WORD16 *out_samples, +VOID ixheaacd_overlap_buf_out_armv7(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac); @@ -132,33 +132,33 @@ WORD32 ixheaacd_inv_quant(WORD32 *x_quant, WORD32 *ixheaacd_pow_table_Q13); VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, WORD32 *ptr_spec_coeff, ia_ics_info_struct *ptr_ics_info, - WORD16 out_samples[], const WORD16 ch_fac, + VOID* out_samples, const WORD16 ch_fac, WORD32 *scratch, ia_aac_dec_tables_struct *ptr_aac_tables, - WORD32 object_type); + WORD32 object_type , WORD slot_element); -VOID ixheaacd_neg_shift_spec_dec(WORD32 *coef, WORD16 *out, WORD16 q_shift, +VOID ixheaacd_neg_shift_spec_dec(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac); -VOID ixheaacd_neg_shift_spec_armv7(WORD32 *coef, WORD16 *out, WORD16 q_shift, +VOID ixheaacd_neg_shift_spec_armv7(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac); -VOID ixheaacd_neg_shift_spec_armv8(WORD32 *coef, WORD16 *out, WORD16 q_shift, +VOID ixheaacd_neg_shift_spec_armv8(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac); VOID ixheaacd_nolap1_32(WORD32 *coef, WORD32 *out, WORD16 cu_scale, WORD16 stride); -VOID ixheaacd_overlap_out_copy_dec(WORD16 *out_samples, WORD32 *ptr_overlap_buf, +VOID ixheaacd_overlap_out_copy_dec(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac); -VOID ixheaacd_overlap_out_copy_armv7(WORD16 *out_samples, +VOID ixheaacd_overlap_out_copy_armv7(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac); -VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD16 *out, +VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD32 *out, const WORD16 *short_window, const WORD16 *short_window_prev, const WORD16 *long_window_prev, WORD16 q_shift, @@ -173,7 +173,7 @@ VOID ixheaacd_huffman_decode(WORD32 it_bit_buff, WORD16 *huff_index, void ixheaacd_eld_dec_windowing(WORD32 *ptr_spect_coeff, const WORD16 *ptr_win, WORD32 framesize, WORD16 q_shift, WORD32 *ptr_overlap_buf, const WORD16 stride, - WORD16 *out_samples); + VOID *out_samples, WORD slot_element); WORD32 ixheaacd_extension_payload(ia_bit_buf_struct *it_bit_buff, WORD32 cnt); @@ -182,8 +182,8 @@ VOID ixheaacd_process_single_scf(WORD32 scale_factor, WORD32 *x_invquant, WORD32 total_channels, WORD32 object_type, WORD32 aac_sf_data_resil_flag); -void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, WORD16 *out, +void ixheaacd_lap1_512_480(WORD32 *coef, WORD32 *prev, VOID *out_tmp, const WORD16 *window, WORD16 q_shift, WORD16 size, - WORD16 stride); + WORD16 stride , WORD slot_element); #endif /* #ifndef IXHEAACD_BLOCK_H */ diff --git a/decoder/ixheaacd_channelinfo.h b/decoder/ixheaacd_channelinfo.h index b582c0e..4cf1216 100644 --- a/decoder/ixheaacd_channelinfo.h +++ b/decoder/ixheaacd_channelinfo.h @@ -43,6 +43,7 @@ typedef struct { WORD16 predictor_data_present; ltp_info ltp; ltp_info ltp2; + WORD8 qshift_adj; } ia_ics_info_struct; typedef struct { diff --git a/decoder/ixheaacd_function_selector.h b/decoder/ixheaacd_function_selector.h index daa5aac..7c6cb94 100644 --- a/decoder/ixheaacd_function_selector.h +++ b/decoder/ixheaacd_function_selector.h @@ -61,7 +61,7 @@ extern VOID (*ixheaacd_covariance_matrix_calc)(WORD32 *, WORD32); extern VOID (*ixheaacd_covariance_matrix_calc_2)( ixheaacd_lpp_trans_cov_matrix *, WORD32 *, WORD32, WORD16); -extern VOID (*ixheaacd_over_lap_add1)(WORD32 *, WORD32 *, WORD16 *, +extern VOID (*ixheaacd_over_lap_add1)(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16); extern VOID (*ixheaacd_over_lap_add2)(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16); @@ -119,19 +119,19 @@ extern WORD32 (*ixheaacd_calc_max_spectral_line)(WORD32 *, WORD32); extern VOID (*ixheaacd_post_twiddle)(WORD32[], WORD32[], ia_aac_dec_imdct_tables_struct *, WORD); -extern VOID (*ixheaacd_post_twid_overlap_add)(WORD16[], WORD32[], +extern VOID (*ixheaacd_post_twid_overlap_add)(WORD32[], WORD32[], ia_aac_dec_imdct_tables_struct *, WORD, WORD32 *, WORD16, const WORD16 *, WORD16); -extern VOID (*ixheaacd_neg_shift_spec)(WORD32 *, WORD16 *, WORD16, WORD16); +extern VOID (*ixheaacd_neg_shift_spec)(WORD32 *, WORD32 *, WORD16, WORD16); extern VOID (*ixheaacd_spec_to_overlapbuf)(WORD32 *, WORD32 *, WORD32, WORD32); -extern VOID (*ixheaacd_overlap_buf_out)(WORD16 *, WORD32 *, WORD32, +extern VOID (*ixheaacd_overlap_buf_out)(WORD32 *, WORD32 *, WORD32, const WORD16); -extern VOID (*ixheaacd_overlap_out_copy)(WORD16 *, WORD32 *, WORD32 *, +extern VOID (*ixheaacd_overlap_out_copy)(WORD32 *, WORD32 *, WORD32 *, const WORD16); extern VOID (*ixheaacd_pretwiddle_compute)(WORD32 *, WORD32 *, WORD32 *, diff --git a/decoder/ixheaacd_lpfuncs.c b/decoder/ixheaacd_lpfuncs.c index 44433a0..c2828bf 100644 --- a/decoder/ixheaacd_lpfuncs.c +++ b/decoder/ixheaacd_lpfuncs.c @@ -120,14 +120,14 @@ static PLATFORM_INLINE WORD32 ixheaacd_mult32x16in32_drc(WORD32 a, WORD16 b) { return (result); } -VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD16 *out, +VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD32 *out, const WORD16 *window_long, const WORD16 *window_short, WORD16 q_shift, WORD16 ch_fac, WORD16 flag) { WORD32 i, accu; WORD32 *coef_1; const WORD16 *temp_win_sh, *temp_win_long; - WORD16 *out1, *out2; + WORD32 *out1, *out2; WORD32 *temp_prev; if (flag == 1) { @@ -137,13 +137,13 @@ VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD16 *out, (q_shift + 1)); accu = ixheaacd_add32_sat(temp1, ((WORD32)prev[i] << 16)); - out[ch_fac * i] = ixheaacd_round16(accu << 1); + out[ch_fac * i] = accu; accu = ixheaacd_shl32_dir_sat_limit( ixheaacd_mult32x16in32(-(coef[SIZE15 - 1 - i]), window_long[2 * (SIZE07 - i) - 1]), q_shift); - out[ch_fac * (i + SIZE09)] = ixheaacd_round16(accu << 2); + out[ch_fac * (i + SIZE09)] = (accu << 1); } temp_win_sh = &(window_short[0]); @@ -158,14 +158,14 @@ VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD16 *out, accu = ixheaacd_mult32x16in32_drc( prev[SIZE08 - 1 - i], ixheaacd_negate16(window_long[2 * i + 1])); - out[ch_fac * i] = ixheaacd_round16(accu << 2); + out[ch_fac * i] = accu; accu = ixheaacd_sub32_sat( ixheaacd_shl32_dir_sat_limit(-(coef[SIZE15 - 1 - i]), (q_shift - 1)), ixheaacd_mult32x16in32_drc(prev[i + SIZE01], window_long[2 * SIZE07 - 2 - 2 * i])); - out[ch_fac * (SIZE09 + i)] = ixheaacd_round16(accu << 2); + out[ch_fac * (SIZE09 + i)] = accu; } temp_win_sh = &(window_long[SIZE14]); @@ -187,7 +187,7 @@ VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD16 *out, ixheaacd_shl32_dir_sat_limit(ixheaacd_mult32x16in32(temp_coef, win1), q_shift), ixheaacd_mult32x16in32_drc(prev1, win3)); - *out1 = ixheaacd_round16(accu << 2); + *out1 = accu << flag; out1 += ch_fac; accu = ixheaacd_sub32_sat( @@ -195,13 +195,13 @@ VOID ixheaacd_process_win_seq(WORD32 *coef, WORD32 *prev, WORD16 *out, ixheaacd_mult32x16in32(ixheaacd_negate32_sat(temp_coef), win2), q_shift), ixheaacd_mult32x16in32_drc(prev1, win4)); - *out2 = ixheaacd_round16(accu << 2); + *out2 = accu << flag; out2 -= ch_fac; } } static PLATFORM_INLINE VOID ixheaacd_long_short_win_process( - WORD32 *current, WORD32 *prev, WORD16 *out, const WORD16 *short_window, + WORD32 *current, WORD32 *prev, WORD32 *out, const WORD16 *short_window, const WORD16 *long_window_prev, WORD16 q_shift, WORD16 ch_fac, WORD32 flag) { WORD i; @@ -220,7 +220,7 @@ static PLATFORM_INLINE VOID ixheaacd_long_short_win_process( ixheaacd_mult32x16in32(tmp2_cur, short1)), q_shift), ixheaacd_mult32x16in32_drc(prev[i], long_window_prev[0 - 2 - 2 * i])); - out[ch_fac * (0 + i)] = ixheaacd_round16(accu << 2); + out[ch_fac * (0 + i)] = accu; if (flag) { accu = ixheaacd_sub32_sat( @@ -230,12 +230,12 @@ static PLATFORM_INLINE VOID ixheaacd_long_short_win_process( q_shift), ixheaacd_mult32x16in32_drc(prev[SIZE02 - 1 - i], long_window_prev[-2 * SIZE02 + 2 * i])); - out[ch_fac * (SIZE02 - 1 - i)] = ixheaacd_round16(accu << 2); + out[ch_fac * (SIZE02 - 1 - i)] = accu; } } } -VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD16 *out, +VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD32 *out, const WORD16 *short_window, const WORD16 *short_window_prev, const WORD16 *long_window_prev, WORD16 q_shift, @@ -245,7 +245,7 @@ VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD16 *out, for (i = 0; i < SIZE07; i++) { accu = ixheaacd_mult32x16in32_drc( prev[SIZE08 - 1 - i], ixheaacd_negate16(long_window_prev[2 * i + 1])); - out[ch_fac * i] = ixheaacd_round16(accu << 2); + out[ch_fac * i] = accu; } for (i = 0; i < SIZE01; i++) { @@ -256,7 +256,7 @@ VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD16 *out, q_shift), ixheaacd_mult32x16in32_drc(prev[SIZE01 - 1 - i], long_window_prev[2 * SIZE07 + 1 + 2 * i])); - out[ch_fac * (SIZE07 + i)] = ixheaacd_round16(accu << 2); + out[ch_fac * (SIZE07 + i)] = accu; } for (i = 0; i < SIZE01; i++) { @@ -267,7 +267,7 @@ VOID ixheaacd_long_short_win_seq(WORD32 *current, WORD32 *prev, WORD16 *out, q_shift), ixheaacd_mult32x16in32_drc(prev[i], long_window_prev[SIZE16 - 2 - (2 * i)])); - out[ch_fac * (SIZE08 + i)] = ixheaacd_round16(accu << 2); + out[ch_fac * (SIZE08 + i)] = accu; } flag = 1; @@ -307,12 +307,11 @@ VOID ixheaacd_nolap1_32(WORD32 *coef, } } -VOID ixheaacd_neg_shift_spec_dec(WORD32 *coef, WORD16 *out, WORD16 q_shift, +VOID ixheaacd_neg_shift_spec_dec(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) { WORD32 i; - for (i = 0; i < SIZE07; i++) { - out[ch_fac * i] = ixheaacd_round16(ixheaacd_shl32_dir_sat_limit( + out[ch_fac * i] = (ixheaacd_shl32_dir_sat_limit( ixheaacd_negate32_sat(coef[SIZE07 - 1 - i]), q_shift)); } } @@ -326,33 +325,34 @@ VOID ixheaacd_spec_to_overlapbuf_dec(WORD32 *ptr_overlap_buf, } } -VOID ixheaacd_overlap_buf_out_dec(WORD16 *out_samples, WORD32 *ptr_overlap_buf, +VOID ixheaacd_overlap_buf_out_dec(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) { WORD32 i; for (i = 0; i < size; i++) { - out_samples[ch_fac * i] = ixheaacd_shl16_sat((WORD16)ptr_overlap_buf[i], 1); + out_samples[ch_fac * i] = + (ixheaacd_shl32_sat((WORD16)ptr_overlap_buf[i], 15)); } } -VOID ixheaacd_overlap_out_copy_dec(WORD16 *out_samples, WORD32 *ptr_overlap_buf, +VOID ixheaacd_overlap_out_copy_dec(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac) { WORD32 i; for (i = 0; i < SIZE01; i++) { - out_samples[ch_fac * i] = ixheaacd_shl16_sat((WORD16)ptr_overlap_buf[i], 1); + out_samples[ch_fac * i] = + ixheaacd_shl32_sat((WORD16)ptr_overlap_buf[i], 15); ptr_overlap_buf[i] = ptr_overlap_buf1[i]; } } VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, WORD32 *ptr_spec_coeff, - ia_ics_info_struct *ptr_ics_info, - WORD16 out_samples[], const WORD16 ch_fac, - WORD32 *scratch, + ia_ics_info_struct *ptr_ics_info, VOID *out_samples, + const WORD16 ch_fac, WORD32 *scratch, ia_aac_dec_tables_struct *ptr_aac_tables, - WORD32 object_type) { + WORD32 object_type, WORD slot_element) { WORD32 *ptr_overlap_buf; const WORD16 *ptr_long_window; const WORD16 *ptr_short_window; @@ -371,6 +371,8 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, if ((512 == ptr_ics_info->frame_length) || (480 == ptr_ics_info->frame_length)) { + ptr_ics_info->qshift_adj = -2; + if (512 == ptr_ics_info->frame_length) { WORD32 *ld_cos_sin_ptr = (WORD32 *)ptr_aac_tables->pstr_imdct_tables->cosine_array_1024; @@ -415,10 +417,13 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, if (1024 == ptr_ics_info->frame_length) { ia_ics_info_struct *tmp_ptr_ics_info = ptr_ics_info; + (*ixheaacd_post_twid_overlap_add)( - out_samples, ptr_spec_coeff, + (WORD32 *)out_samples, ptr_spec_coeff, ptr_aac_tables->pstr_imdct_tables, 1024, ptr_overlap_buf, q_shift, ptr_long_window, ch_fac); + + ptr_ics_info->qshift_adj = 2; ptr_ics_info = tmp_ptr_ics_info; } if ((512 == ptr_ics_info->frame_length) || @@ -426,21 +431,24 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, if (object_type != AOT_ER_AAC_ELD) { if (512 == ptr_ics_info->frame_length) { ixheaacd_lap1_512_480(ptr_spec_coeff, ptr_overlap_buf, - out_samples, ptr_long_window, q_shift, - SIZE04, ch_fac); + (WORD16 *)out_samples, ptr_long_window, + q_shift, SIZE04, ch_fac, slot_element); ixheaacd_spec_to_overlapbuf(ptr_overlap_buf, ptr_spec_coeff, q_shift, SIZE04); } else if (480 == ptr_ics_info->frame_length) { ixheaacd_lap1_512_480(ptr_spec_coeff, ptr_overlap_buf, - out_samples, ptr_long_window, q_shift, - 240, ch_fac); + (WORD16 *)out_samples, ptr_long_window, + q_shift, 240, ch_fac, slot_element); ixheaacd_spec_to_overlapbuf(ptr_overlap_buf, ptr_spec_coeff, q_shift, 240); } } else { - ixheaacd_eld_dec_windowing( - ptr_spec_coeff, ptr_long_window, ptr_ics_info->frame_length, - q_shift, ptr_overlap_buf, ch_fac, out_samples); + ixheaacd_eld_dec_windowing(ptr_spec_coeff, ptr_long_window, + ptr_ics_info->frame_length, q_shift, + ptr_overlap_buf, ch_fac, + (WORD16 *)out_samples, slot_element); + + ptr_ics_info->qshift_adj = -2; } } break; @@ -452,9 +460,10 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, ptr_aac_tables->pstr_imdct_tables, 1024); } - ixheaacd_process_win_seq(scratch, ptr_overlap_buf, out_samples, - ptr_long_window, ptr_short_window, q_shift, - ch_fac, 1); + ixheaacd_process_win_seq(scratch, ptr_overlap_buf, + (WORD32 *)out_samples, ptr_long_window, + ptr_short_window, q_shift, ch_fac, 1); + ptr_ics_info->qshift_adj = 1; if (512 == ptr_ics_info->frame_length) { ixheaacd_spec_to_overlapbuf(ptr_overlap_buf, ptr_spec_coeff, @@ -480,17 +489,20 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, case ONLY_LONG_SEQUENCE: case LONG_STOP_SEQUENCE: - (*ixheaacd_over_lap_add1)(scratch, ptr_overlap_buf, out_samples, - ptr_long_window, q_shift, SIZE08, ch_fac); + (*ixheaacd_over_lap_add1)(scratch, ptr_overlap_buf, + (WORD32 *)out_samples, ptr_long_window, + q_shift, SIZE08, ch_fac); + ptr_ics_info->qshift_adj = 2; break; case LONG_START_SEQUENCE: case EIGHT_SHORT_SEQUENCE: - ixheaacd_process_win_seq(scratch, ptr_overlap_buf, out_samples, - ptr_long_window, ptr_short_window, q_shift, - ch_fac, 1); + ixheaacd_process_win_seq(scratch, ptr_overlap_buf, + (WORD32 *)out_samples, ptr_long_window, + ptr_short_window, q_shift, ch_fac, 1); + ptr_ics_info->qshift_adj = 1; break; } @@ -512,28 +524,32 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, case EIGHT_SHORT_SEQUENCE: case LONG_START_SEQUENCE: - (*ixheaacd_overlap_buf_out)(out_samples, ptr_overlap_buf, SIZE07, - ch_fac); + (*ixheaacd_overlap_buf_out)((WORD32 *)out_samples, ptr_overlap_buf, + SIZE07, ch_fac); (*ixheaacd_over_lap_add1)( &scratch[SIZE14], &ptr_overlap_buf[SIZE07], - &out_samples[ch_fac * (SIZE07)], ptr_short_window, q_shift, - SIZE01, ch_fac); + ((WORD32 *)out_samples + ch_fac * (SIZE07)), ptr_short_window, + q_shift, SIZE01, ch_fac); { - WORD16 q_shift1 = q_shift + 1; - (*ixheaacd_neg_shift_spec)(&scratch[SIZE08], - &out_samples[ch_fac * SIZE09], - q_shift1, ch_fac); + WORD16 q_shift1 = q_shift - 1; + + (*ixheaacd_neg_shift_spec)( + &scratch[SIZE08], ((WORD32 *)out_samples + ch_fac * SIZE09), + q_shift1, ch_fac); } + ptr_ics_info->qshift_adj = 2; break; case ONLY_LONG_SEQUENCE: case LONG_STOP_SEQUENCE: - ixheaacd_process_win_seq(scratch, ptr_overlap_buf, out_samples, - ptr_long_window, ptr_short_window, q_shift, - ch_fac, 0); + ixheaacd_process_win_seq(scratch, ptr_overlap_buf, + (WORD32 *)out_samples, ptr_long_window, + ptr_short_window, q_shift, ch_fac, 0); + + ptr_ics_info->qshift_adj = 2; break; } @@ -579,11 +595,11 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, case EIGHT_SHORT_SEQUENCE: case LONG_START_SEQUENCE: - (*ixheaacd_overlap_buf_out)(out_samples, ptr_overlap_buf, SIZE07, - ch_fac); + (*ixheaacd_overlap_buf_out)((WORD32 *)out_samples, ptr_overlap_buf, + SIZE07, ch_fac); (*ixheaacd_over_lap_add1)(&scratch[0], &ptr_overlap_buf[SIZE07], - &out_samples[ch_fac * SIZE07], + ((WORD32 *)out_samples + ch_fac * SIZE07), ptr_short_window, q_shift, SIZE01, ch_fac); for (i = 0; i < 3; i++) { @@ -591,27 +607,32 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, (*ixheaacd_spec_to_overlapbuf)(overlap_buf_loc, &scratch[inc], q_shift, SIZE01); - (*ixheaacd_over_lap_add1)(&scratch[SIZE02 + inc], overlap_buf_loc, - &out_samples[ch_fac * (SIZE09 + inc)], - short_window, q_shift, SIZE01, ch_fac); + (*ixheaacd_over_lap_add1)( + &scratch[SIZE02 + inc], overlap_buf_loc, + ((WORD32 *)out_samples + ch_fac * (SIZE09 + inc)), short_window, + q_shift, SIZE01, ch_fac); } (*ixheaacd_over_lap_add2)(&scratch[SIZE08], &scratch[SIZE06], ptr_overlap_buf, short_window, q_shift, SIZE01, 1); - (*ixheaacd_overlap_out_copy)(&out_samples[ch_fac * SIZE15], + (*ixheaacd_overlap_out_copy)(((WORD32 *)out_samples + ch_fac * SIZE15), ptr_overlap_buf, &ptr_overlap_buf[SIZE01], ch_fac); + ptr_ics_info->qshift_adj = 2; + break; case ONLY_LONG_SEQUENCE: case LONG_STOP_SEQUENCE: - ixheaacd_long_short_win_seq(scratch, ptr_overlap_buf, out_samples, - short_window, ptr_short_window, - ptr_long_window, q_shift, ch_fac); + ixheaacd_long_short_win_seq( + scratch, ptr_overlap_buf, (WORD32 *)out_samples, short_window, + ptr_short_window, ptr_long_window, q_shift, ch_fac); + + ptr_ics_info->qshift_adj = 2; break; } @@ -633,7 +654,7 @@ VOID ixheaacd_imdct_process(ia_aac_dec_overlap_info *ptr_aac_dec_overlap_info, void ixheaacd_eld_dec_windowing(WORD32 *ptr_spect_coeff, const WORD16 *p_win, WORD32 framesize, WORD16 q_shift, WORD32 *p_overlap_buffer, const WORD16 stride, - WORD16 *out_samples) + VOID *out_samples_t, WORD slot_element) { int i = 0; @@ -644,6 +665,8 @@ void ixheaacd_eld_dec_windowing(WORD32 *ptr_spect_coeff, const WORD16 *p_win, WORD32 *p_overlap_buffer32 = (WORD32 *)p_overlap_buffer; WORD32 delay = framesize >> 2; + WORD16 *out_samples = (WORD16 *)out_samples_t - slot_element; + ptr_z = ptr_spect_coeff + delay; p_win += delay; ptr_out = p_overlap_buffer32; diff --git a/decoder/ixheaacd_lt_predict.c b/decoder/ixheaacd_lt_predict.c index 83fc9cc..9f5b852 100644 --- a/decoder/ixheaacd_lt_predict.c +++ b/decoder/ixheaacd_lt_predict.c @@ -396,15 +396,18 @@ VOID ixheaacd_filter_bank_ltp(ia_aac_dec_tables_struct *aac_tables_ptr, } } -VOID ixheaacd_lt_update_state(WORD16 *lt_pred_stat, WORD16 *time, +VOID ixheaacd_lt_update_state(WORD16 *lt_pred_stat, void *time_t, WORD32 *overlap, WORD32 frame_len, WORD32 object_type, WORD32 stride, - WORD16 window_sequence, WORD16 *p_window_next) { + WORD16 window_sequence, WORD16 *p_window_next, + WORD slot_element) { WORD32 i; + if (object_type == AOT_ER_AAC_LD) { WORD16 *ptr_ltp_state0 = <_pred_stat[0]; WORD16 *ptr_ltp_state_fl = <_pred_stat[frame_len + 0]; WORD16 *ptr_ltp_state_2fl = <_pred_stat[(frame_len * 2) + 0]; + WORD16 *time = (WORD16 *)time_t - slot_element; WORD16 *ptr_time_in = &time[0 * stride]; for (i = 0; i < frame_len; i++) { @@ -417,11 +420,15 @@ VOID ixheaacd_lt_update_state(WORD16 *lt_pred_stat, WORD16 *time, } else { WORD16 *ptr_ltp_state0 = <_pred_stat[0]; WORD16 *ptr_ltp_state_fl = <_pred_stat[frame_len + 0]; - WORD16 *ptr_time_in = &time[0 * stride]; + WORD32 *time = (WORD32 *)time_t; + WORD32 *ptr_time_in = &time[0 * stride]; + + time = (WORD32 *)time_t; for (i = 0; i < frame_len; i++) { *ptr_ltp_state0++ = *ptr_ltp_state_fl; - *ptr_ltp_state_fl++ = *ptr_time_in; + *ptr_ltp_state_fl++ = + ixheaacd_round16(ixheaacd_shl32_sat(*ptr_time_in, 2)); ptr_time_in += stride; } } diff --git a/decoder/ixheaacd_lt_predict.h b/decoder/ixheaacd_lt_predict.h index 8e4fbfc..69a2a39 100644 --- a/decoder/ixheaacd_lt_predict.h +++ b/decoder/ixheaacd_lt_predict.h @@ -46,10 +46,10 @@ typedef struct { VOID ixheaacd_init_ltp_object(ltp_info *ltp); -VOID ixheaacd_lt_update_state(WORD16 *lt_pred_stat, WORD16 *time, - WORD32 *overlap, WORD32 frame_len, - WORD32 object_type, WORD32 stride, - WORD16 window_sequence, WORD16 *p_window_next); +VOID ixheaacd_lt_update_state(WORD16 *lt_pred_stat, void *time, WORD32 *overlap, + WORD32 frame_len, WORD32 object_type, + WORD32 stride, WORD16 window_sequence, + WORD16 *p_window_next, WORD slot_element); VOID ixheaacd_filter_bank_ltp(ia_aac_dec_tables_struct *aac_tables_ptr, WORD16 window_sequence, WORD16 win_shape, diff --git a/decoder/ixheaacd_multichannel.c b/decoder/ixheaacd_multichannel.c index d914ad2..998c194 100644 --- a/decoder/ixheaacd_multichannel.c +++ b/decoder/ixheaacd_multichannel.c @@ -255,35 +255,37 @@ IA_ERRORCODE ixheaacd_dec_coupling_channel_element( return error_status; } -void ixheaacd_dec_couple_channel(WORD16 *p_time_data, WORD16 *out_samp_cc, +void ixheaacd_dec_couple_channel(WORD32 *p_time_data, WORD32 *out_samp_cc, WORD16 frame_size, WORD total_channels, - WORD32 gain_cc) + WORD16 gain_cc) { WORD i; - WORD16 out_cc; - WORD16 *ptr_out_samp = &out_samp_cc[0]; + WORD32 out_cc; + WORD32 *ptr_out_samp = &out_samp_cc[0]; for (i = frame_size - 1; i >= 0; i--) { - out_cc = ixheaacd_round16(ixheaacd_shl32_sat( - ixheaacd_mult32x16in32(gain_cc, *ptr_out_samp++), 3)); - *p_time_data = ixheaacd_add16_sat(out_cc, *p_time_data); + out_cc = (ixheaacd_shl32_sat( + ixheaacd_mult32x16in32(*ptr_out_samp++, gain_cc), 3)); + *p_time_data = ixheaacd_add32_sat(out_cc, *p_time_data); p_time_data += total_channels; } } void ixheaacd_dec_ind_coupling( - ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec, WORD16 *coup_ch_output, - WORD16 frame_size, WORD total_channels, WORD16 *ptr_time_data) + ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec, WORD32 *coup_ch_output, + WORD16 frame_size, WORD total_channels, VOID *ptr_time_data_tmp) { WORD c, j, k; WORD l; WORD coupling_channel; - WORD16 *out_samp_cc; + WORD32 *out_samp_cc; ia_enhaacplus_dec_ind_cc *ind_channel_info; + WORD32 *ptr_time_data = (WORD32 *)ptr_time_data_tmp; + { coupling_channel = p_obj_exhaacplus_dec->aac_config.ui_coupling_channel; @@ -308,18 +310,18 @@ void ixheaacd_dec_ind_coupling( k = p_obj_exhaacplus_dec->aac_config.slot_element[l]; if (ind_channel_info->cc_target_is_cpe[c] == 0) { - WORD16 *p_time_data = &ptr_time_data[k]; + WORD32 *p_time_data = &ptr_time_data[k]; - WORD32 gain_cc = ind_channel_info->cc_gain[j]; + WORD16 gain_cc = ixheaacd_round16(ind_channel_info->cc_gain[j]); ixheaacd_dec_couple_channel(p_time_data, out_samp_cc, frame_size, total_channels, gain_cc); } if (ind_channel_info->cc_target_is_cpe[c] == 1) { if (ind_channel_info->cc_l[c] == 1) { - WORD16 *p_time_data = &ptr_time_data[k]; + WORD32 *p_time_data = &ptr_time_data[k]; - WORD32 gain_cc = ind_channel_info->cc_gain[j]; + WORD16 gain_cc = ixheaacd_round16(ind_channel_info->cc_gain[j]); ixheaacd_dec_couple_channel(p_time_data, out_samp_cc, frame_size, total_channels, gain_cc); @@ -328,8 +330,8 @@ void ixheaacd_dec_ind_coupling( k = p_obj_exhaacplus_dec->aac_config.slot_element[l]; if (ind_channel_info->cc_r[c] == 1) { - WORD16 *p_time_data = &ptr_time_data[k + 1]; - WORD32 gain_cc = ind_channel_info->cc_gain[j + 1]; + WORD32 *p_time_data = &ptr_time_data[k + 1]; + WORD16 gain_cc = ixheaacd_round16(ind_channel_info->cc_gain[j + 1]); ixheaacd_dec_couple_channel(p_time_data, out_samp_cc, frame_size, total_channels, gain_cc); diff --git a/decoder/ixheaacd_multichannel.h b/decoder/ixheaacd_multichannel.h index 9156f44..f641421 100644 --- a/decoder/ixheaacd_multichannel.h +++ b/decoder/ixheaacd_multichannel.h @@ -29,11 +29,11 @@ IA_ERRORCODE ixheaacd_dec_coupling_channel_element( ia_eld_specific_config_struct eld_specific_config, WORD32 ele_type); void ixheaacd_dec_ind_coupling( - ia_exhaacplus_dec_api_struct *p_obj_enhaacplus_dec, WORD16 *coup_ch_output, - WORD16 frame_size, WORD total_channels, WORD16 *ptr_time_data); + ia_exhaacplus_dec_api_struct *p_obj_enhaacplus_dec, WORD32 *coup_ch_output, + WORD16 frame_size, WORD total_channels, VOID *ptr_time_data); void ixheaacd_dec_downmix_to_stereo( ia_exhaacplus_dec_api_struct *p_obj_enhaacplus_dec, WORD16 frame_size, WORD total_elements, WORD16 *ptr_time_data, WORD total_channels); -#endif /* IA_EAACP_DEC_MUTLCHANNEL_H */ \ No newline at end of file +#endif /* IA_EAACP_DEC_MUTLCHANNEL_H */ diff --git a/decoder/ixheaacd_peak_limiter.c b/decoder/ixheaacd_peak_limiter.c new file mode 100644 index 0000000..9c99e94 --- /dev/null +++ b/decoder/ixheaacd_peak_limiter.c @@ -0,0 +1,206 @@ +/****************************************************************************** + * * + * Copyright (C) 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ***************************************************************************** + * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore +*/ +#include +#include +#include +#include "ixheaacd_cnst.h" +#include "ixheaacd_peak_limiter_struct_def.h" +#include "ixheaacd_constants.h" +#include "ixheaacd_basic_ops32.h" +#include "ixheaacd_basic_ops16.h" + +#define MAX(x, y) ((x) > (y) ? (x) : (y)) +#define MIN(x, y) ((x) > (y) ? (y) : (x)) + +/** +* ixheaacd_peak_limiter_init +* +* \brief Peak Limiter initialization +* +* \param [in/out] peak_limiter Pointer to peak_limiter struct +* \param [in] num_channels Number of ouptut channels +* \param [in] sample_rate Sampling rate value +* \param [in] buffer Peak limiter buffer of size PEAK_LIM_BUFFER_SIZE +* +* \return WORD32 +* +*/ +WORD32 ixheaacd_peak_limiter_init(ia_peak_limiter_struct *peak_limiter, + UWORD32 num_channels, UWORD32 sample_rate, + FLOAT32 *buffer, UWORD32 *delay_in_samples) { + UWORD32 attack; + + attack = (UWORD32)(DEFAULT_ATTACK_TIME_MS * sample_rate / 1000); + *delay_in_samples = attack; + + if (attack < 1) return 0; + + peak_limiter->max_buf = buffer; + peak_limiter->max_idx = 0; + peak_limiter->cir_buf_pnt = 0; + peak_limiter->delayed_input = buffer + attack + 1; + + peak_limiter->delayed_input_index = 0; + peak_limiter->attack_time = DEFAULT_ATTACK_TIME_MS; + peak_limiter->release_time = DEFAULT_RELEASE_TIME_MS; + peak_limiter->attack_time_samples = attack; + peak_limiter->attack_constant = (FLOAT32)pow(0.1, 1.0 / (attack + 1)); + peak_limiter->release_constant = (FLOAT32)pow( + 0.1, 1.0 / (DEFAULT_RELEASE_TIME_MS * sample_rate / 1000 + 1)); + peak_limiter->num_channels = num_channels; + peak_limiter->sample_rate = sample_rate; + peak_limiter->min_gain = 1.0f; + peak_limiter->limiter_on = 1; + peak_limiter->pre_smoothed_gain = 1.0f; + peak_limiter->gain_modified = 1.0f; + + return 0; +} + +/** +* ixheaacd_peak_limiter_process +* +* \brief Peak Limiter process +* +* \param [in/out] peak_limiter +* \param [in] samples +* \param [in] frame_len +* +* \return WORD32 +* +*/ +VOID ixheaacd_peak_limiter_process(ia_peak_limiter_struct *peak_limiter, + VOID *samples_t, UWORD32 frame_len, + UWORD8 *qshift_adj) { + UWORD32 i, j; + FLOAT32 tmp, gain; + FLOAT32 min_gain = 1.0f; + FLOAT32 maximum; + UWORD32 num_channels = peak_limiter->num_channels; + UWORD32 attack_time_samples = peak_limiter->attack_time_samples; + FLOAT32 attack_constant = peak_limiter->attack_constant; + FLOAT32 release_constant = peak_limiter->release_constant; + FLOAT32 *max_buf = peak_limiter->max_buf; + FLOAT32 gain_modified = peak_limiter->gain_modified; + FLOAT32 *delayed_input = peak_limiter->delayed_input; + UWORD32 delayed_input_index = peak_limiter->delayed_input_index; + FLOAT64 pre_smoothed_gain = peak_limiter->pre_smoothed_gain; + WORD32 limit_threshold = 2147483647; + + WORD32 *samples = (WORD32 *)samples_t; + + if (peak_limiter->limiter_on || (FLOAT32)pre_smoothed_gain) { + for (i = 0; i < frame_len; i++) { + tmp = 0.0f; + for (j = 0; j < num_channels; j++) { + FLOAT32 gain_t = (FLOAT32)(1 << *(qshift_adj + j)); + tmp = MAX(tmp, fabs((samples[i * num_channels + j] * gain_t))); + } + max_buf[peak_limiter->cir_buf_pnt] = tmp; + + if (peak_limiter->max_idx == peak_limiter->cir_buf_pnt) { + peak_limiter->max_idx = 0; + for (j = 1; j < (attack_time_samples); j++) { + if (max_buf[j] > max_buf[peak_limiter->max_idx]) + peak_limiter->max_idx = j; + } + } else if (tmp >= max_buf[peak_limiter->max_idx]) { + peak_limiter->max_idx = peak_limiter->cir_buf_pnt; + } + peak_limiter->cir_buf_pnt++; + + if (peak_limiter->cir_buf_pnt == (WORD32)(attack_time_samples)) + peak_limiter->cir_buf_pnt = 0; + maximum = max_buf[peak_limiter->max_idx]; + + if (maximum > limit_threshold) { + gain = limit_threshold / maximum; + } else { + gain = 1; + } + + if (gain < pre_smoothed_gain) { + gain_modified = + MIN(gain_modified, + (gain - 0.1f * (FLOAT32)pre_smoothed_gain) * 1.11111111f); + + } else { + gain_modified = gain; + } + + if (gain_modified < pre_smoothed_gain) { + pre_smoothed_gain = + attack_constant * (pre_smoothed_gain - gain_modified) + + gain_modified; + pre_smoothed_gain = MAX(pre_smoothed_gain, gain); + } else { + pre_smoothed_gain = + release_constant * (pre_smoothed_gain - gain_modified) + + gain_modified; + } + + gain = (FLOAT32)pre_smoothed_gain; + + for (j = 0; j < num_channels; j++) { + WORD64 tmp_fix; + tmp = delayed_input[delayed_input_index * num_channels + j]; + FLOAT32 gain_t = (FLOAT32)(1 << *(qshift_adj + j)); + delayed_input[delayed_input_index * num_channels + j] = + samples[i * num_channels + j] * gain_t; + + tmp *= gain; + + tmp_fix = tmp; + + if (tmp_fix > limit_threshold) + tmp_fix = limit_threshold; + else if (tmp_fix < -limit_threshold) + tmp_fix = -limit_threshold; + + samples[i * num_channels + j] = tmp_fix; + } + + delayed_input_index++; + if (delayed_input_index >= attack_time_samples) delayed_input_index = 0; + + if (gain < min_gain) min_gain = gain; + } + } else { + for (i = 0; i < frame_len; i++) { + for (j = 0; j < num_channels; j++) { + tmp = delayed_input[delayed_input_index * num_channels + j]; + FLOAT32 gain_t = (FLOAT32)(1 << *(qshift_adj + j)); + delayed_input[delayed_input_index * num_channels + j] = + samples[i * num_channels + j] * gain_t; + samples[i * num_channels + j] = tmp; + } + + delayed_input_index++; + if (delayed_input_index >= attack_time_samples) delayed_input_index = 0; + } + } + + peak_limiter->gain_modified = gain_modified; + peak_limiter->delayed_input_index = delayed_input_index; + peak_limiter->pre_smoothed_gain = pre_smoothed_gain; + peak_limiter->min_gain = min_gain; + + return; +} diff --git a/decoder/ixheaacd_peak_limiter_struct_def.h b/decoder/ixheaacd_peak_limiter_struct_def.h new file mode 100644 index 0000000..1241418 --- /dev/null +++ b/decoder/ixheaacd_peak_limiter_struct_def.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * * + * Copyright (C) 2018 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ***************************************************************************** + * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore +*/ +#ifndef IXHEAACD_PEAK_LIMITER_STRUCT_DEF_H +#define IXHEAACD_PEAK_LIMITER_STRUCT_DEF_H + +#define MAX_CHANNEL 6 +/*(PEAK_LIM_SIZE = ATTACK_TIME * MAX_SAMPLING_RATE / 1000) + 1*/ +#define PEAK_LIM_SIZE 481 +#define PEAK_LIM_BUFFER_SIZE PEAK_LIM_SIZE *(MAX_CHANNEL + 1) + +#define DEFAULT_ATTACK_TIME_MS (5.0f) +#define DEFAULT_RELEASE_TIME_MS (50.0f) + +typedef struct ia_peak_limiter_struct { + FLOAT32 attack_time; + FLOAT32 release_time; + FLOAT32 attack_constant; + FLOAT32 release_constant; + FLOAT32 limit_threshold; + UWORD32 num_channels; + UWORD32 sample_rate; + UWORD32 attack_time_samples; + UWORD32 limiter_on; + FLOAT32 gain_modified; + FLOAT64 pre_smoothed_gain; + FLOAT32 *delayed_input; + UWORD32 delayed_input_index; + FLOAT32 *max_buf; + FLOAT32 min_gain; + FLOAT32 buffer[PEAK_LIM_BUFFER_SIZE]; + WORD32 max_idx; + WORD32 cir_buf_pnt; +} ia_peak_limiter_struct; + +#endif /* IXHEAACD_PEAK_LIMITER_STRUCT_DEF_H */ diff --git a/decoder/ixheaacd_process.c b/decoder/ixheaacd_process.c index f1c7202..7ace0ca 100644 --- a/decoder/ixheaacd_process.c +++ b/decoder/ixheaacd_process.c @@ -94,7 +94,9 @@ VOID ixheaacd_allocate_sbr_scr(ia_sbr_scr_struct *sbr_scratch_struct, VOID *base_scratch_ptr, VOID *output_ptr, WORD total_elements, WORD ch_fac, - WORD32 object_type); + WORD32 object_type, WORD32 total_channels, + WORD8 *p_qshift_arr, UWORD8 slot_element, + WORD32 channel); IA_ERRORCODE ixheaacd_applysbr( ia_handle_sbr_dec_inst_struct self, @@ -117,7 +119,7 @@ IA_ERRORCODE ixheaacd_esbr_process(ia_usac_data_struct *usac_data, ia_sbr_scr_struct sbr_scratch_struct; ixheaacd_allocate_sbr_scr(&sbr_scratch_struct, usac_data->sbr_scratch_mem_base, NULL, 2, 1, - audio_object_type); + audio_object_type, 0, NULL, 0, 0); self->usac_independency_flag = usac_data->usac_independency_flg; diff --git a/decoder/ixheaacd_struct_def.h b/decoder/ixheaacd_struct_def.h index 3a52867..f7fe3fe 100644 --- a/decoder/ixheaacd_struct_def.h +++ b/decoder/ixheaacd_struct_def.h @@ -22,6 +22,7 @@ #include #include +#include "ixheaacd_peak_limiter_struct_def.h" #define MAX_OUTPUT_CHANNELS (8) #define MAX_NUM_OTT (1) @@ -144,6 +145,7 @@ typedef struct { ia_drc_config drc_config_struct; WORD32 output_level; WORD32 i_loud_ref_level; + UWORD8 dup_stereo_flag; } ia_aac_dec_config_struct; @@ -187,7 +189,7 @@ typedef struct ia_aac_dec_state_struct { WORD32 last_frame_ok; WORD32 i_bytes_consumed; - WORD16 *coup_ch_output; + WORD32 *coup_ch_output; ia_enhaacplus_dec_ind_cc ind_cc_info; WORD8 protection_absent; @@ -246,6 +248,15 @@ typedef struct ia_aac_dec_state_struct { WORD8 *pers_mem_ptr; bool preroll_config_present; UWORD8 preroll_config_prev[MAX_PREROLL_SIZE]; + + UWORD8 qshift_cnt; + WORD8 qshift_adj[16]; + UWORD32 delay_in_samples; + UWORD8 peak_lim_init; + ia_peak_limiter_struct peak_limiter; + UWORD8 sbr_present; + UWORD8 slot_pos; + } ia_aac_dec_state_struct; typedef struct ia_exhaacplus_dec_api_struct { @@ -265,14 +276,14 @@ typedef struct ia_exhaacplus_dec_api_struct { WORD32 ixheaacd_aacdec_decodeframe( ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec, - ia_aac_dec_scratch_struct *aac_scratch_ptrs, WORD16 *time_data, + ia_aac_dec_scratch_struct *aac_scratch_ptrs, VOID *time_data, FLAG frame_status, WORD *type, WORD *ch_idx, WORD init_flag, WORD channel, WORD *element_index_order, WORD skip_full_decode, WORD ch_fac, WORD slot_element, WORD max_channels, WORD32 total_channels, WORD32 frame_length, WORD32 frame_size, ia_drc_dec_struct *pstr_drc_dec, WORD32 object_type, WORD32 ch_config, ia_eld_specific_config_struct eld_specific_config, WORD16 adtsheader, - ia_drc_dec_struct *drc_dummy); + ia_drc_dec_struct *drc_dummy, UWORD8 *slot_pos); WORD ixheaacd_get_channel_mask( ia_exhaacplus_dec_api_struct *p_obj_exhaacplus_dec); diff --git a/decoder/x86/ixheaacd_function_selector_x86.c b/decoder/x86/ixheaacd_function_selector_x86.c index f9c71fa..72c88df 100644 --- a/decoder/x86/ixheaacd_function_selector_x86.c +++ b/decoder/x86/ixheaacd_function_selector_x86.c @@ -74,7 +74,7 @@ VOID(*ixheaacd_covariance_matrix_calc_2) WORD16) = &ixheaacd_covariance_matrix_calc_2_dec; VOID(*ixheaacd_over_lap_add1) -(WORD32 *, WORD32 *, WORD16 *, const WORD16 *, WORD16, WORD16, +(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16) = &ixheaacd_over_lap_add1_dec; VOID(*ixheaacd_over_lap_add2) @@ -159,13 +159,13 @@ VOID(*ixheaacd_post_twiddle) WORD npoints) = &ixheaacd_post_twiddle_dec; VOID(*ixheaacd_post_twid_overlap_add) -(WORD16 pcm_out[], WORD32 spec_data[], +(WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) = &ixheaacd_post_twid_overlap_add_dec; VOID(*ixheaacd_neg_shift_spec) -(WORD32 *coef, WORD16 *out, WORD16 q_shift, +(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) = &ixheaacd_neg_shift_spec_dec; VOID(*ixheaacd_spec_to_overlapbuf) @@ -173,11 +173,11 @@ VOID(*ixheaacd_spec_to_overlapbuf) WORD32 size) = &ixheaacd_spec_to_overlapbuf_dec; VOID(*ixheaacd_overlap_buf_out) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) = &ixheaacd_overlap_buf_out_dec; VOID(*ixheaacd_overlap_out_copy) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac) = &ixheaacd_overlap_out_copy_dec; VOID(*ixheaacd_pretwiddle_compute) @@ -246,4 +246,4 @@ VOID(*ixheaacd_inv_dit_fft_8pt) VOID(*ixheaacd_scale_factor_process) (WORD32 *x_invquant, WORD16 *scale_fact, WORD no_band, WORD8 *width, WORD32 *scale_tables_ptr, WORD32 total_channels, WORD32 object_type, - WORD32 aac_sf_data_resil_flag) = &ixheaacd_scale_factor_process_dec; \ No newline at end of file + WORD32 aac_sf_data_resil_flag) = &ixheaacd_scale_factor_process_dec; diff --git a/decoder/x86_64/ixheaacd_function_selector_x86_64.c b/decoder/x86_64/ixheaacd_function_selector_x86_64.c index f9c71fa..72c88df 100644 --- a/decoder/x86_64/ixheaacd_function_selector_x86_64.c +++ b/decoder/x86_64/ixheaacd_function_selector_x86_64.c @@ -74,7 +74,7 @@ VOID(*ixheaacd_covariance_matrix_calc_2) WORD16) = &ixheaacd_covariance_matrix_calc_2_dec; VOID(*ixheaacd_over_lap_add1) -(WORD32 *, WORD32 *, WORD16 *, const WORD16 *, WORD16, WORD16, +(WORD32 *, WORD32 *, WORD32 *, const WORD16 *, WORD16, WORD16, WORD16) = &ixheaacd_over_lap_add1_dec; VOID(*ixheaacd_over_lap_add2) @@ -159,13 +159,13 @@ VOID(*ixheaacd_post_twiddle) WORD npoints) = &ixheaacd_post_twiddle_dec; VOID(*ixheaacd_post_twid_overlap_add) -(WORD16 pcm_out[], WORD32 spec_data[], +(WORD32 pcm_out[], WORD32 spec_data[], ia_aac_dec_imdct_tables_struct *ptr_imdct_tables, WORD npoints, WORD32 *ptr_overlap_buf, WORD16 q_shift, const WORD16 *window, WORD16 ch_fac) = &ixheaacd_post_twid_overlap_add_dec; VOID(*ixheaacd_neg_shift_spec) -(WORD32 *coef, WORD16 *out, WORD16 q_shift, +(WORD32 *coef, WORD32 *out, WORD16 q_shift, WORD16 ch_fac) = &ixheaacd_neg_shift_spec_dec; VOID(*ixheaacd_spec_to_overlapbuf) @@ -173,11 +173,11 @@ VOID(*ixheaacd_spec_to_overlapbuf) WORD32 size) = &ixheaacd_spec_to_overlapbuf_dec; VOID(*ixheaacd_overlap_buf_out) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 size, const WORD16 ch_fac) = &ixheaacd_overlap_buf_out_dec; VOID(*ixheaacd_overlap_out_copy) -(WORD16 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, +(WORD32 *out_samples, WORD32 *ptr_overlap_buf, WORD32 *ptr_overlap_buf1, const WORD16 ch_fac) = &ixheaacd_overlap_out_copy_dec; VOID(*ixheaacd_pretwiddle_compute) @@ -246,4 +246,4 @@ VOID(*ixheaacd_inv_dit_fft_8pt) VOID(*ixheaacd_scale_factor_process) (WORD32 *x_invquant, WORD16 *scale_fact, WORD no_band, WORD8 *width, WORD32 *scale_tables_ptr, WORD32 total_channels, WORD32 object_type, - WORD32 aac_sf_data_resil_flag) = &ixheaacd_scale_factor_process_dec; \ No newline at end of file + WORD32 aac_sf_data_resil_flag) = &ixheaacd_scale_factor_process_dec;