diff --git a/decoder/armv7/ixheaacd_apply_rot.s b/decoder/armv7/ixheaacd_apply_rot.s index ef3b13f..f6d91f5 100644 --- a/decoder/armv7/ixheaacd_apply_rot.s +++ b/decoder/armv7/ixheaacd_apply_rot.s @@ -25,7 +25,7 @@ ixheaacd_apply_rot_armv7: STMFD SP!, {R4-R12, R14} - LDR R5, =0x59e + MOVW R5, #0x59e MOV R4, #22 ADD R11, R0, R5 LOOP1: @@ -70,7 +70,7 @@ LOOP1: BGT LOOP1 - LDR R4, =0x53C + MOVW R4, #0x53C LDR R12, [R0, #44] ADD R11, R0, R4 MOV R4, #10 @@ -116,8 +116,8 @@ LOOP2: BGT LOOP2 - LDR R11, =0x6c2 - LDR R5, =0x564 + MOVW R11, #0x6c2 + MOVW R5, #0x564 LDRSH R14, [R0, R11] ADD R11, R0, R5 LDR R5, [SP, #44] diff --git a/decoder/armv7/ixheaacd_complex_fft_p2.s b/decoder/armv7/ixheaacd_complex_fft_p2.s index 89efa8a..564f304 100644 --- a/decoder/armv7/ixheaacd_complex_fft_p2.s +++ b/decoder/armv7/ixheaacd_complex_fft_p2.s @@ -20,8 +20,10 @@ ixheaacd_complex_fft_p2_asm: MOV r0, #0 FIRST_STAGE_R4: - LDR r4, =0x33333333 - LDR r5, =0x0F0F0F0F + MOVW r4, #0x3333 + MOVT r4, #0x3333 + MOVW r5, #0x0F0F + MOVT r5, #0x0F0F AND r6, r4, r0 AND r7, r4, r0, LSR #2 ORR r4, r7, r6, LSL #2 diff --git a/decoder/armv7/ixheaacd_complex_ifft_p2.s b/decoder/armv7/ixheaacd_complex_ifft_p2.s index 3a0ce5a..61765be 100644 --- a/decoder/armv7/ixheaacd_complex_ifft_p2.s +++ b/decoder/armv7/ixheaacd_complex_ifft_p2.s @@ -20,8 +20,10 @@ ixheaacd_complex_ifft_p2_asm: MOV r0, #0 FIRST_STAGE_R4: - LDR r4, =0x33333333 - LDR r5, =0x0F0F0F0F + MOVW r4, #0x3333 + MOVT r4, #0x3333 + MOVW r5, #0x0F0F + MOVT r5, #0x0F0F AND r6, r4, r0 AND r7, r4, r0, LSR #2 ORR r4, r7, r6, LSL #2 diff --git a/decoder/armv7/ixheaacd_conv_ergtoamplitude.s b/decoder/armv7/ixheaacd_conv_ergtoamplitude.s index f46464c..e7ab0ee 100644 --- a/decoder/armv7/ixheaacd_conv_ergtoamplitude.s +++ b/decoder/armv7/ixheaacd_conv_ergtoamplitude.s @@ -28,8 +28,8 @@ ixheaacd_conv_ergtoamplitude_armv7: LDR R5, [SP, #44] LDR R4, [SP, #40] - LDR R14, =0x1FF - LDR R10, =0x5A82 + MOVW R14, #0x1FF + MOVW R10, #0x5A82 LOOP1: diff --git a/decoder/armv7/ixheaacd_conv_ergtoamplitudelp.s b/decoder/armv7/ixheaacd_conv_ergtoamplitudelp.s index 193b116..95200d5 100644 --- a/decoder/armv7/ixheaacd_conv_ergtoamplitudelp.s +++ b/decoder/armv7/ixheaacd_conv_ergtoamplitudelp.s @@ -28,8 +28,8 @@ ixheaacd_conv_ergtoamplitudelp_armv7: LDR R5, [SP, #44] LDR R4, [SP, #40] - LDR R11, =0x5A82 - LDR R10, =0x1FF + MOVW R11, #0x5A82 + MOVW R10, #0x1FF LOOP1: diff --git a/decoder/armv7/ixheaacd_decorr_filter2.s b/decoder/armv7/ixheaacd_decorr_filter2.s index b6529ed..bddae5d 100644 --- a/decoder/armv7/ixheaacd_decorr_filter2.s +++ b/decoder/armv7/ixheaacd_decorr_filter2.s @@ -742,7 +742,7 @@ DE_COR_NEXT1: MOV r7, r13 LDR r3, [r0, #0x020] LDR r4, [r0, #0x028] - LDR r12, =0x620a + MOVW r12, #0x620a LDR r6, [r0, #0x024] STR r0, [r13, #-4]! STR r5, [r13, #-4]! diff --git a/decoder/armv7/ixheaacd_esbr_fwd_modulation.s b/decoder/armv7/ixheaacd_esbr_fwd_modulation.s index 98beeec..82fb546 100644 --- a/decoder/armv7/ixheaacd_esbr_fwd_modulation.s +++ b/decoder/armv7/ixheaacd_esbr_fwd_modulation.s @@ -63,7 +63,7 @@ LOOP1: LDR R4, [SP, #124] MOV R0, R1 MOV R1, R3 - ldr R5, =0x41FC + MOVW R5, #0x41FC ADD R2, R4, R5 ADD R3, R4, #0xB8 diff --git a/decoder/armv7/ixheaacd_fft32x32_ld2_armv7.s b/decoder/armv7/ixheaacd_fft32x32_ld2_armv7.s index f09ba65..80e62b3 100644 --- a/decoder/armv7/ixheaacd_fft32x32_ld2_armv7.s +++ b/decoder/armv7/ixheaacd_fft32x32_ld2_armv7.s @@ -198,9 +198,12 @@ ixheaacd_fft32x32_ld2_armv7: @Load twiddle factors - LDR r11, =2310960706 @0x89BE7642 - LDR r12, =3473158396 @0xCF0430FC - LDR r14, =2776455811 @0xA57D5A83 + MOVW r11, 0X7642 + MOVT r11, 0X89BE + MOVW r12, 0X30FC + MOVT r12, 0XCF04 + MOVW r14, 0X5A83 + MOVT r14, 0XA57D @Second Butterfly LDR r2, [r0, #32] @mul_0qr = inp_0qr = x[8] diff --git a/decoder/armv7/ixheaacd_fft_15_ld.s b/decoder/armv7/ixheaacd_fft_15_ld.s index df9e3e6..5e245b6 100644 --- a/decoder/armv7/ixheaacd_fft_15_ld.s +++ b/decoder/armv7/ixheaacd_fft_15_ld.s @@ -1,12 +1,5 @@ -.equ C53_VAL , -11904 -.equ SINMU_VAL , 28378 -.equ C51_52VAL , 0x79BC9D84 -.equ C54_55VAL , 0x478EB000 -.equ FFTOP_OFFSET , -1536 -.equ FFTOP_OFFSET1 , 256 - .text .p2align 2 .global ixheaacd_fft_15_ld_armv7 @@ -34,7 +27,8 @@ LOOP_FFT5: ADD r1, r4, r10 @ r1 = buf1a[2] + buf1a[8] SUB r4, r4, r10 @ r4 = buf1a[2] - buf1a[8]@ - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r12, r6, r8 @ r3 = buf1a[4] + buf1a[6] SUB r8, r6, r8 @ r2 = buf1a[4] - buf1a[6] @@ -44,7 +38,8 @@ LOOP_FFT5: ADD r2, r2, r1 @ temp1 = inp[0] + r1@ SMULWB r1, r1, r10 @ mult32_shl(r1, C55) ADD r1, r2, r1, lsl #2 @ r1 = temp1 + ((mult32_shl(r1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r2, [lr], #4 @ *buf2++ = temp1@ SUB r12, r1, r6, LSL #1 @ r3 = r1 - t@ @@ -57,7 +52,8 @@ LOOP_FFT5: MOV r2, r2, LSL #1 SMULWB r4, r4, r10 @ mult32_shl(r4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r4, r2, r4, LSL #2 @ r4 = t + (mult32_shl(r4, C52) << 1)@ SMULWB r8, r8, r10 @ mult32_shl(r2, C53) @@ -65,7 +61,8 @@ LOOP_FFT5: ADD r6, r5, r11 @ s1 = buf1a[3] + buf1a[9] SUB r8, r5, r11 @ s4 = buf1a[3] - buf1a[9] - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r5, r7, r9 @ s3 = buf1a[5] + buf1a[7]@ SUB r7, r7, r9 @ s2 = buf1a[5] + buf1a[7]@ @@ -76,7 +73,8 @@ LOOP_FFT5: ADD r3, r3, r6 @ temp2 = buf1a[1] + s1 SMULWB r6, r6, r10 @ mult32_shl(s1, C55) ADD r6, r3, r6, lsl #2 @ s1 = temp1 + ((mult32_shl(s1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r3, [lr], #4 @ *buf2++ = temp2@ SUB r5, r6, r9, LSL #1 @ s3 = s1 - t@ @@ -90,7 +88,8 @@ LOOP_FFT5: SMULWB r8, r8, r10 @ mult32_shl(s4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r8, r11, r8, LSL #2 @ s4 = t + (mult32_shl(s4, C52) << 1)@ SMULWB r7, r7, r10 @ mult32_shl(s2, C53) @@ -108,7 +107,8 @@ LOOP_FFT5: STMIA lr!, {r3, r9-r12} @ MOV r12, #384 @ - LDR r1, = FFTOP_OFFSET @ + MOVW r1, #0xFA00 + MOVT r1, #0xFFFF STMIA lr!, {r4-r6} @ @@ -126,7 +126,8 @@ LOOP_FFT5: ADD r1, r4, r10 @ r1 = buf1a[2] + buf1a[8] SUB r4, r4, r10 @ r4 = buf1a[2] - buf1a[8]@ - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r12, r6, r8 @ r3 = buf1a[4] + buf1a[6] SUB r8, r6, r8 @ r2 = buf1a[4] - buf1a[6] @@ -136,7 +137,8 @@ LOOP_FFT5: ADD r2, r2, r1 @ temp1 = inp[0] + r1@ SMULWB r1, r1, r10 @ mult32_shl(r1, C55) ADD r1, r2, r1, lsl #2 @ r1 = temp1 + ((mult32_shl(r1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r2, [lr], #4 @ *buf2++ = temp1@ SUB r12, r1, r6, LSL #1 @ r3 = r1 - t@ @@ -149,7 +151,8 @@ LOOP_FFT5: SMULWB r4, r4, r10 @ mult32_shl(r4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r4, r2, r4, LSL #2 @ r4 = t + (mult32_shl(r4, C52) << 1)@ SMULWB r8, r8, r10 @ mult32_shl(r2, C53) @@ -157,7 +160,8 @@ LOOP_FFT5: ADD r6, r5, r11 @ s1 = buf1a[3] + buf1a[9] SUB r8, r5, r11 @ s4 = buf1a[3] - buf1a[9] - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r5, r7, r9 @ s3 = buf1a[5] + buf1a[7]@ SUB r7, r7, r9 @ s2 = buf1a[5] + buf1a[7]@ @@ -168,7 +172,8 @@ LOOP_FFT5: ADD r3, r3, r6 @ temp2 = buf1a[1] + s1 SMULWB r6, r6, r10 @ mult32_shl(s1, C55) ADD r6, r3, r6, lsl #2 @ s1 = temp1 + ((mult32_shl(s1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r3, [lr], #4 @ *buf2++ = temp2@ @@ -181,7 +186,8 @@ LOOP_FFT5: MOV r11, r11, LSL #1 SMULWB r8, r8, r10 @mult32_shl(s4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r8, r11, r8, LSL #2 @s4 = t + (mult32_shl(s4, C52) << 1)@ SMULWB r7, r7, r10 @mult32_shl(s2, C53) @@ -195,7 +201,8 @@ LOOP_FFT5: SUB r4, r5, r4 @buf2[7] = s3 - r4 SUB r5, r1, r7 @buf2[8] = r1 - s2 ADD r6, r6, r2 @buf2[9] = s1 + r2 - LDR r1, = FFTOP_OFFSET @ + MOVW r1, #0xFA00 + MOVT r1, #0xFFFF STMIA lr!, {r3, r9-r12} MOV r12, #384 @ @@ -215,7 +222,8 @@ LOOP_FFT5: ADD r1, r4, r10 @ r1 = buf1a[2] + buf1a[8] SUB r4, r4, r10 @ r4 = buf1a[2] - buf1a[8]@ - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r12, r6, r8 @ r3 = buf1a[4] + buf1a[6] SUB r8, r6, r8 @ r2 = buf1a[4] - buf1a[6] @@ -225,7 +233,8 @@ LOOP_FFT5: ADD r2, r2, r1 @ temp1 = inp[0] + r1@ SMULWB r1, r1, r10 @ mult32_shl(r1, C55) ADD r1, r2, r1, lsl #2 @ r1 = temp1 + ((mult32_shl(r1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r2, [lr], #4 @ *buf2++ = temp1@ SUB r12, r1, r6, LSL #1 @ r3 = r1 - t@ @@ -237,7 +246,8 @@ LOOP_FFT5: MOV r2, r2, LSL #1 SMULWB r4, r4, r10 @ mult32_shl(r4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r4, r2, r4, LSL #2 @ r4 = t + (mult32_shl(r4, C52) << 1)@ SMULWB r8, r8, r10 @ mult32_shl(r2, C53) @@ -245,7 +255,8 @@ LOOP_FFT5: ADD r6, r5, r11 @ s1 = buf1a[3] + buf1a[9] SUB r8, r5, r11 @ s4 = buf1a[3] - buf1a[9] - LDR r10, = C54_55VAL + MOVW r10, #0xB000 + MOVT r10, #0x478E ADD r5, r7, r9 @ s3 = buf1a[5] + buf1a[7]@ SUB r7, r7, r9 @ s2 = buf1a[5] + buf1a[7]@ @@ -255,7 +266,8 @@ LOOP_FFT5: ADD r3, r3, r6 @ temp2 = buf1a[1] + s1 SMULWB r6, r6, r10 @ mult32_shl(s1, C55) ADD r6, r3, r6, lsl #2 @ s1 = temp1 + ((mult32_shl(s1, C55)) << 1)@ - LDR r10, = C51_52VAL @ + MOVW r10, #0x9D84 + MOVT r10, #0x79BC STR r3, [lr], #4 @ *buf2++ = temp2@ SUB r5, r6, r9, LSL #1 @ s3 = s1 - t@ @@ -267,7 +279,8 @@ LOOP_FFT5: MOV r11, r11, LSL #1 SMULWB r8, r8, r10 @mult32_shl(s4, C52) - LDR r10, = C53_VAL + MOVW r10, #0xD180 + MOVT r10, #0xFFFF ADD r8, r11, r8, LSL #2 @s4 = t + (mult32_shl(s4, C52) << 1)@ @@ -287,7 +300,7 @@ LOOP_FFT5: STMIA lr!, {r4-r6} @ SUB lr, lr, #120 @ - LDR r12, = SINMU_VAL @ + MOVW r12, # 28378 @ LDMFD r13!, {r10, r11} @ diff --git a/decoder/armv7/ixheaacd_imdct_using_fft.s b/decoder/armv7/ixheaacd_imdct_using_fft.s index 563c041..86689d8 100644 --- a/decoder/armv7/ixheaacd_imdct_using_fft.s +++ b/decoder/armv7/ixheaacd_imdct_using_fft.s @@ -33,13 +33,13 @@ ixheaacd_imdct_using_fft_armv7: @ LDR r6, [sp, #0x68+8] @ LDR r7, [sp, #0x68+12] - LDR r8, =11600 + MOVW r8, #11600 ADD r4, r0, r8 - LDR r8, =11856 + MOVW r8, #11856 ADD r5, r0, r8 - LDR r8, =11920 + MOVW r8, #11920 ADD r6, r0, r8 - LDR r8, =11936 + MOVW r8, #11936 ADD r7, r0, r8 @@ -278,7 +278,7 @@ RADIX_8_FIRST_LOOP: VUZP.16 d28, d29 VADD.S32 q4, q8, q7 - LDR r14, =0x5a82 + MOVW r14, #0x5a82 VSUB.S32 q11, q8, q7 @@ -615,7 +615,7 @@ RADIX_4_FIRST_ENDS: PUSH {r3} LSR r5, r5, #2 - LDR r14, =8528 + MOVW r14, #8528 ADD r0, r0, r14 OUTER_LOOP_R4: diff --git a/decoder/armv7/ixheaacd_inv_dit_fft_8pt.s b/decoder/armv7/ixheaacd_inv_dit_fft_8pt.s index 7ed90d9..a4fd00d 100644 --- a/decoder/armv7/ixheaacd_inv_dit_fft_8pt.s +++ b/decoder/armv7/ixheaacd_inv_dit_fft_8pt.s @@ -114,7 +114,7 @@ ixheaacd_inv_dit_fft_8pt_armv7: QADD r7, lr, r10 QSUB r10, lr, r10 - LDR r11, =0x00005a82 + MOVW r11, #0x00005a82 STR r10, [r2, #0x10] QSUB r10, r8, r0 diff --git a/decoder/armv7/ixheaacd_post_twiddle.s b/decoder/armv7/ixheaacd_post_twiddle.s index 4d9d2dd..fe48fda 100644 --- a/decoder/armv7/ixheaacd_post_twiddle.s +++ b/decoder/armv7/ixheaacd_post_twiddle.s @@ -32,7 +32,7 @@ ixheaacd_post_twiddle_armv7: ARM_PROLOGUE: CMP R3, #0x400 - LDR R6, =7500 + MOVW R6, #7500 ADD R2, R2, R6 BLT NEXT MOV R4, #50 @@ -43,8 +43,8 @@ ARM_PROLOGUE: B NEXT1 NEXT: - LDR R4, =0x192 - LDR R5, =0xfe6e + MOVW R4, #0x192 + MOVW R5, #0xfe6e MOV R6, #32 VDUP.16 D10, R4 diff --git a/decoder/armv7/ixheaacd_post_twiddle_overlap.s b/decoder/armv7/ixheaacd_post_twiddle_overlap.s index 391e1c6..24a5ba3 100644 --- a/decoder/armv7/ixheaacd_post_twiddle_overlap.s +++ b/decoder/armv7/ixheaacd_post_twiddle_overlap.s @@ -37,7 +37,7 @@ ixheaacd_post_twid_overlap_add_armv7: ADD R6, R6, R9 SUB R6, R6, #4 - LDR R8, =7500 + MOVW R8, #7500 ADD R2, R2, R8 diff --git a/decoder/armv7/ixheaacd_pre_twiddle_compute.s b/decoder/armv7/ixheaacd_pre_twiddle_compute.s index 6cc22aa..e65f1da 100644 --- a/decoder/armv7/ixheaacd_pre_twiddle_compute.s +++ b/decoder/armv7/ixheaacd_pre_twiddle_compute.s @@ -28,7 +28,7 @@ ixheaacd_pretwiddle_compute_armv7: STMFD sp!, {R4-R12} VPUSH {d8 - d15} - LDR R8, =7500 + MOVW R8, #7500 ADD R3, R3, R8 LDR R4, [sp, #100] LDR R5, [sp, #104] diff --git a/decoder/armv7/ixheaacd_sbr_imdct_using_fft.s b/decoder/armv7/ixheaacd_sbr_imdct_using_fft.s index d398eb7..5fe89e0 100644 --- a/decoder/armv7/ixheaacd_sbr_imdct_using_fft.s +++ b/decoder/armv7/ixheaacd_sbr_imdct_using_fft.s @@ -282,7 +282,7 @@ RADIX_8_FIRST_LOOP: VUZP.16 d28, d29 VADD.S32 q4, q8, q7 - LDR r14, =0x5a82 + MOVW r14, #0x5a82 VSUB.S32 q11, q8, q7 diff --git a/decoder/armv8/ixheaacd_cos_sin_mod_loop1.s b/decoder/armv8/ixheaacd_cos_sin_mod_loop1.s index bbd55df..4a0d235 100644 --- a/decoder/armv8/ixheaacd_cos_sin_mod_loop1.s +++ b/decoder/armv8/ixheaacd_cos_sin_mod_loop1.s @@ -45,7 +45,7 @@ ixheaacd_cos_sin_mod_loop1: SUB x5, x5, #8 ASR x6, x1, #2 - LDR w19, =0 + MOV w19, #0 DUP V0.8h, w19 LOOP1: //first part @@ -83,7 +83,7 @@ LOOP1: ADD x3, x3, #8 ADD x7, x3, #248 ST2 {v2.s, v3.s}[2], [x7] - LDR w19, =0 + MOV w19, #0 DUP V0.8h, w19 //second part ld1 {v0.h}[0] , [x2] @@ -120,7 +120,7 @@ LOOP1: ADD x7, x5, #256 ST2 {v2.s, v3.s}[2], [x7] SUB x5, x5, #8 - LDR w19, =0 + MOV w19, #0 DUP V0.8h, w19 //Third part ld1 {v0.h}[0] , [x2] @@ -156,7 +156,7 @@ LOOP1: ADD x3, x3, #8 ADD x7, x3, #248 ST2 {v2.s, v3.s}[2], [x7] - LDR w19, =0 + MOV w19, #0 DUP V0.8h, w19 //Fourth part ld1 {v0.h}[0] , [x2] @@ -195,7 +195,7 @@ LOOP1: SUBS x6, x6, #1 ST2 {v2.s, v3.s}[2], [x7] SUB x5, x5, #8 - LDR w19, =0 + MOV w19, #0 DUP V0.8h, w19 BGT LOOP1 //VPOP {D8-D11} diff --git a/decoder/armv8/ixheaacd_cos_sin_mod_loop2.s b/decoder/armv8/ixheaacd_cos_sin_mod_loop2.s index a48a705..e51cd58 100644 --- a/decoder/armv8/ixheaacd_cos_sin_mod_loop2.s +++ b/decoder/armv8/ixheaacd_cos_sin_mod_loop2.s @@ -45,7 +45,7 @@ ixheaacd_cos_sin_mod_loop2: ADD x11, x10, x2, LSL #3 SUB x11, x11, #4 MOV x8, #-4 - LDR w19, =0 + MOV w19, #0 DUP V0.4s, w19 DUP V1.4s, w19 @@ -164,7 +164,7 @@ LOOP1: ST1 {v12.s}[2], [x11], x8 ST1 {v16.s}[2], [x10], #4 - LDR w19, =0 + MOV w19, #0 DUP V0.4s, w19 DUP V1.4s, w19 // second part diff --git a/decoder/armv8/ixheaacd_fft32x32_ld2_armv8.s b/decoder/armv8/ixheaacd_fft32x32_ld2_armv8.s index b20aa46..280164b 100644 --- a/decoder/armv8/ixheaacd_fft32x32_ld2_armv8.s +++ b/decoder/armv8/ixheaacd_fft32x32_ld2_armv8.s @@ -266,19 +266,19 @@ ixheaacd_fft32x32_ld2_armv8: //Load twiddle factors // LDR w11, =2310960706 //0x89BE7642 - LDR w11, =0x7642 + MOV w11, #0x7642 sxth w11, w11 - LDR w21, =0x89BE + MOV w21, #0x89BE sxth w21, w21 // LDR w12, =3473158396 //0xCF0430FC - LDR w12, =0x30FC + MOV w12, #0x30FC sxth w12, w12 - LDR w22, =0xCF04 + MOV w22, #0xCF04 sxth w22, w22 // LDR w14, =2776455811 //0xA57D5A83 - LDR w14, =0x5A83 + MOV w14, #0x5A83 sxth w14, w14 - LDR w24, =0xA57D + MOV w24, #0xA57D sxth w24, w24 //Second Butterfly diff --git a/decoder/armv8/ixheaacd_imdct_using_fft.s b/decoder/armv8/ixheaacd_imdct_using_fft.s index 9f2e204..8f8916a 100644 --- a/decoder/armv8/ixheaacd_imdct_using_fft.s +++ b/decoder/armv8/ixheaacd_imdct_using_fft.s @@ -55,13 +55,13 @@ ixheaacd_imdct_using_fft_armv8: push_v_regs - LDR X29, =11600 + MOV X29, #11600 ADD X4, X0, X29 - LDR X29, =11856 + MOV X29, #11856 ADD X5, X0, X29 - LDR X29, =11920 + MOV X29, #11920 ADD X6, X0, X29 - LDR X29, =11936 + MOV X29, #11936 ADD X7, X0, X29 COND_1: CMP X1, #0x400 @@ -611,7 +611,7 @@ RADIX_4_FIRST_ENDS: MOv x30, X3 LSR X5, X5, #2 - LDR X14, =8528 + MOV X14, #8528 ADD X0, X0, X14 OUTER_LOOP_R4: diff --git a/decoder/armv8/ixheaacd_inv_dit_fft_8pt.s b/decoder/armv8/ixheaacd_inv_dit_fft_8pt.s index 51deed7..197a825 100644 --- a/decoder/armv8/ixheaacd_inv_dit_fft_8pt.s +++ b/decoder/armv8/ixheaacd_inv_dit_fft_8pt.s @@ -20,7 +20,7 @@ .global ixheaacd_inv_dit_fft_8pt_armv8 ixheaacd_inv_dit_fft_8pt_armv8: push_v_regs - LDR w3, =0x5A820000 + MOV w3, #0x5A820000 DUP v0.2s, w3 MOV x5, #8 ADD x6, x0, #4 diff --git a/decoder/armv8/ixheaacd_post_twiddle.s b/decoder/armv8/ixheaacd_post_twiddle.s index 2e7f6d4..c28b9da 100644 --- a/decoder/armv8/ixheaacd_post_twiddle.s +++ b/decoder/armv8/ixheaacd_post_twiddle.s @@ -49,7 +49,7 @@ ixheaacd_post_twiddle_armv8: ARM_PROLOGUE: CMP w3, #0x400 - LDR x21, =7500 + MOV x21, #7500 ADD x2, x2, x21 BLT NEXT MOV w4, #50 diff --git a/decoder/armv8/ixheaacd_post_twiddle_overlap.s b/decoder/armv8/ixheaacd_post_twiddle_overlap.s index 8ddce48..b8ee331 100644 --- a/decoder/armv8/ixheaacd_post_twiddle_overlap.s +++ b/decoder/armv8/ixheaacd_post_twiddle_overlap.s @@ -65,7 +65,7 @@ ixheaacd_post_twid_overlap_add_armv8: ADD x6, x6, x9 SUB x6, x6, #4 - LDR w8, =7500 + MOV w8, #7500 sxtw x8, w8 ADD x2, x2, x8 @@ -185,9 +185,9 @@ ARM_PROLOGUE: BGE NEXT2 CMN x8, #1 NEXT2: - LDR x20, =0x80000000 + MOV x20, #0x80000000 csel x7, x20, x7, LT - LDR x20, =0x7fffffff + MOV x20, #0x7fffffff csel x7, x20, x7, GT LSL x20, x7, x11 csel x7, x20, x7, EQ @@ -200,9 +200,9 @@ NEXT2: BGE NEXT3 CMN x8, #1 NEXT3: - LDR x20, =0x80000000 + MOV x20, #0x80000000 csel x12, x20, x12, LT - LDR x20, =0x7fffffff + MOV x20, #0x7fffffff csel x12, x20, x12, GT LSL x20, x12, x11 csel x12, x20, x12, EQ diff --git a/decoder/armv8/ixheaacd_pre_twiddle.s b/decoder/armv8/ixheaacd_pre_twiddle.s index 7fae0bd..7c02ba5 100644 --- a/decoder/armv8/ixheaacd_pre_twiddle.s +++ b/decoder/armv8/ixheaacd_pre_twiddle.s @@ -59,7 +59,7 @@ ixheaacd_pretwiddle_compute_armv8: LSL x7, x4, #4 ADD x7, x2, x7 SUB x7, x7, #4 - LDR x22, =7500 + MOV x22, #7500 ADD x3, x3, x22 MVN w5, w5 ADD w5, w5, #1 diff --git a/decoder/drc_src/impd_drc_api.c b/decoder/drc_src/impd_drc_api.c index 65e54a6..4fea3de 100644 --- a/decoder/drc_src/impd_drc_api.c +++ b/decoder/drc_src/impd_drc_api.c @@ -435,6 +435,9 @@ IA_ERRORCODE ia_drc_dec_api(pVOID p_ia_drc_dec_obj, WORD32 i_cmd, WORD32 i_idx, break; } case IA_API_CMD_SET_MEMTABS_PTR: { + if (ps_value == NULL) return IA_DRC_DEC_API_FATAL_MEM_ALLOC; + memset(ps_value, 0, + (sizeof(ia_mem_info_struct) + sizeof(pVOID *)) * (NUM_DRC_TABLES)); p_obj_drc->p_mem_info = (ia_mem_info_struct *)(ps_value); p_obj_drc->pp_mem = (pVOID)((SIZE_T)p_obj_drc->p_mem_info + @@ -560,8 +563,6 @@ IA_ERRORCODE impd_drc_mem_api(ia_drc_api_struct *p_obj_drc, WORD32 i_cmd, break; } case IA_API_CMD_SET_MEM_PTR: { - pWORD8 pbtemp; - UWORD32 sz; if (pv_value == 0) { return (-1); } @@ -569,12 +570,10 @@ IA_ERRORCODE impd_drc_mem_api(ia_drc_api_struct *p_obj_drc, WORD32 i_cmd, return (-1); } p_obj_drc->pp_mem[i_idx] = pv_value; - pbtemp = p_obj_drc->pp_mem[i_idx]; - sz = p_obj_drc->p_mem_info[i_idx].ui_size; + memset(p_obj_drc->pp_mem[i_idx], 0, p_obj_drc->p_mem_info[i_idx].ui_size); if (IA_MEMTYPE_PERSIST == i_idx) { p_obj_drc->p_state = pv_value; } - memset(pbtemp, 0, sz); break; } case IA_API_CMD_SET_MEM_PLACEMENT: { diff --git a/decoder/drc_src/impd_drc_init.c b/decoder/drc_src/impd_drc_init.c index 14830ed..b4711c8 100644 --- a/decoder/drc_src/impd_drc_init.c +++ b/decoder/drc_src/impd_drc_init.c @@ -89,6 +89,7 @@ static WORD32 impd_match_downmix(WORD32 downmix_id, WORD32 dec_downmix_id) { } IA_ERRORCODE impd_drc_set_default_config(ia_drc_api_struct *p_obj_drc) { + memset(p_obj_drc, 0, sizeof(*p_obj_drc)); p_obj_drc->str_config.bitstream_file_format = 0; p_obj_drc->str_config.dec_type = 0; p_obj_drc->str_config.sub_band_domain_mode = 0; diff --git a/decoder/ixheaacd_aacdec.h b/decoder/ixheaacd_aacdec.h index ec1af57..8f161eb 100644 --- a/decoder/ixheaacd_aacdec.h +++ b/decoder/ixheaacd_aacdec.h @@ -23,7 +23,6 @@ #define AAC_DEC_OK IA_ENHAACPLUS_DEC_API_NONFATAL_NO_ERROR #define IA_ENHAACPDEC_NUM_MEMTABS (4) -#define IA_MPS_DEC_NUM_MEMTABS (4) #define FRAME_SIZE 1024 diff --git a/decoder/ixheaacd_api.c b/decoder/ixheaacd_api.c index f4e5bfb..1947a24 100644 --- a/decoder/ixheaacd_api.c +++ b/decoder/ixheaacd_api.c @@ -150,9 +150,6 @@ IA_ERRORCODE ixheaacd_dec_mem_api( sizeof(ia_audio_specific_config_struct) + (8300)); p_obj_exhaacplus_dec->p_state_aac = pv_value; - memset(p_obj_exhaacplus_dec->p_state_aac, 0, - sizeof(ia_aac_dec_state_struct)); - p_obj_exhaacplus_dec->p_state_aac->pstr_dec_data = p_temp; p_obj_exhaacplus_dec->p_state_aac->ia_audio_specific_config = p_temp + sizeof(ia_dec_data_struct); @@ -781,10 +778,14 @@ IA_ERRORCODE ixheaacd_dec_api(pVOID p_ia_enhaacplus_dec_obj, WORD32 i_cmd, case IA_API_CMD_GET_MEMTABS_SIZE: { *pui_value = (sizeof(ia_mem_info_struct) + sizeof(pVOID *)) * - (IA_ENHAACPDEC_NUM_MEMTABS + IA_MPS_DEC_NUM_MEMTABS); + (IA_ENHAACPDEC_NUM_MEMTABS); break; } case IA_API_CMD_SET_MEMTABS_PTR: { + if (pv_value == NULL) return IA_ENHAACPLUS_DEC_API_FATAL_MEM_ALLOC; + memset(pv_value, 0, (sizeof(ia_mem_info_struct) + sizeof(pVOID *)) * + (IA_ENHAACPDEC_NUM_MEMTABS)); + p_obj_exhaacplus_dec->p_mem_info_aac = pv_value; p_obj_exhaacplus_dec->pp_mem_aac = (pVOID *)((WORD8 *)pv_value + diff --git a/libxaac_blacklist.txt b/libxaac_blacklist.txt index be2f594..f7c61b7 100644 --- a/libxaac_blacklist.txt +++ b/libxaac_blacklist.txt @@ -108,5 +108,6 @@ fun:ixheaacd_mdct_480_ld fun:ixheaacd_mps_synt_calc fun:ixheaacd_read_spectral_data fun:ixheaacd_tns_apply - - +fun:ixheaacd_cplx_synt_qmffilt +fun:ixheaacd_sbr_qmfsyn64_winadd +fun:ixheaacd_filt_8_ch diff --git a/test/ixheaacd_main.c b/test/ixheaacd_main.c index baa490c..fef904e 100644 --- a/test/ixheaacd_main.c +++ b/test/ixheaacd_main.c @@ -924,7 +924,6 @@ int ixheaacd_main_process(WORD32 argc, pWORD8 argv[]) { /* Allocate memory for API */ g_pv_arr_alloc_memory[g_w_malloc_count] = malloc(pui_api_size + 4); - memset(g_pv_arr_alloc_memory[g_w_malloc_count], 0, pui_api_size); if (g_pv_arr_alloc_memory[g_w_malloc_count] == NULL) { _IA_HANDLE_ERROR(&ixheaacd_ia_testbench_error_info, (pWORD8) "API struct alloc", err_code);