diff --git a/common/arm/ihevc_sao_edge_offset_class3_chroma.s b/common/arm/ihevc_sao_edge_offset_class3_chroma.s
index 6561a8a..62f40d1 100644
--- a/common/arm/ihevc_sao_edge_offset_class3_chroma.s
+++ b/common/arm/ihevc_sao_edge_offset_class3_chroma.s
@@ -703,9 +703,9 @@ WD_16_HT_4_LOOP:
 
 SKIP_AU1_MASK_VAL_WD_16_HT_4:
     LDRB        r11,[r5,#2]                 @pu1_avail[2]
+    CMP         r11,#0
     SUBEQ       r8,r0,r1                    @pu1_src - src_strd
 
-    CMP         r11,#0
     MOVNE       r8,r3
     VLD1.8      D12,[r0]!                   @pu1_cur_row = vld1q_u8(pu1_src)
     VLD1.8      D13,[r0]                    @pu1_cur_row = vld1q_u8(pu1_src)
diff --git a/common/arm64/ihevc_sao_edge_offset_class3_chroma.s b/common/arm64/ihevc_sao_edge_offset_class3_chroma.s
index 8e93110..7c9dfd8 100644
--- a/common/arm64/ihevc_sao_edge_offset_class3_chroma.s
+++ b/common/arm64/ihevc_sao_edge_offset_class3_chroma.s
@@ -775,9 +775,9 @@ WD_16_HT_4_LOOP:
 SKIP_AU1_MASK_VAL_WD_16_HT_4:
     LDRB        w11,[x5,#2]                 //pu1_avail[2]
     SUB         x20,x0,x1                   //pu1_src - src_strd
+    CMP         x11,#0
     csel        x8, x20, x8,EQ
 
-    CMP         x11,#0
     csel        x8, x3, x8,NE
     LD1         {v5.16b},[x0]               //pu1_cur_row = vld1q_u8(pu1_src)
     //LD1 {v13.8b},[x0]                        //pu1_cur_row = vld1q_u8(pu1_src)