bb0f31cb6b
Added support for encoding 'Scalable Baseline' profile, corresponding to profile_idc of 83 in 'Rec. ITU-T H.264 (11/2007)'. Bug: 248891908 Test: svcenc -c enc.cfg Change-Id: Ib12ca4c4a8c0e674738ae2af01558a08cefe0929
125 lines
4.3 KiB
C
125 lines
4.3 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2022 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*****************************************************************************
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* Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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*/
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/**
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******************************************************************************
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* @file
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* isvce_core_coding.h
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*
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* @brief
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* This file contains extern declarations of core coding routines
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*
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* @author
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* ittiam
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*
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* @remarks
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* none
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******************************************************************************
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*/
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#ifndef _ISVCE_CORE_CODING_H_
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#define _ISVCE_CORE_CODING_H_
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#include "isvce_structs.h"
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/*****************************************************************************/
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/* Constant Macros */
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/*****************************************************************************/
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/**
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******************************************************************************
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* @brief Enable/Disable Hadamard transform of DC Coeff's
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******************************************************************************
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*/
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#define DISABLE_DC_TRANSFORM 0
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#define ENABLE_DC_TRANSFORM 1
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/**
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*******************************************************************************
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* @brief bit masks for DC and AC control flags
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*******************************************************************************
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*/
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#define DC_COEFF_CNT_LUMA_MB 16
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#define NUM_4X4_BLKS_LUMA_MB_ROW 4
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#define NUM_LUMA4x4_BLOCKS_IN_MB 16
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#define NUM_CHROMA4x4_BLOCKS_IN_MB 8
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#define SIZE_4X4_BLK_HRZ TRANS_SIZE_4
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#define SIZE_4X4_BLK_VERT TRANS_SIZE_4
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#define CNTRL_FLAG_DC_MASK_LUMA 0x0000FFFF
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#define CNTRL_FLAG_AC_MASK_LUMA 0xFFFF0000
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#define CNTRL_FLAG_AC_MASK_CHROMA_U 0xF0000000
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#define CNTRL_FLAG_DC_MASK_CHROMA_U 0x0000F000
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#define CNTRL_FLAG_AC_MASK_CHROMA_V 0x0F000000
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#define CNTRL_FLAG_DC_MASK_CHROMA_V 0x00000F00
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#define CNTRL_FLAG_AC_MASK_CHROMA (CNTRL_FLAG_AC_MASK_CHROMA_U | CNTRL_FLAG_AC_MASK_CHROMA_V)
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#define CNTRL_FLAG_DC_MASK_CHROMA (CNTRL_FLAG_DC_MASK_CHROMA_U | CNTRL_FLAG_DC_MASK_CHROMA_V)
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#define CNTRL_FLAG_DCBLK_MASK_CHROMA 0x0000C000
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/**
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*******************************************************************************
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* @brief macros for transforms
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*******************************************************************************
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*/
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#define DEQUEUE_BLKID_FROM_CONTROL(u4_cntrl, blk_lin_id) \
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{ \
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blk_lin_id = CLZ(u4_cntrl); \
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u4_cntrl &= (0x7FFFFFFF >> blk_lin_id); \
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};
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#define IND2SUB_LUMA_MB(u4_blk_id, i4_offset_x, i4_offset_y) \
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{ \
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i4_offset_x = (u4_blk_id % 4) << 2; \
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i4_offset_y = (u4_blk_id / 4) << 2; \
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}
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#define IS_V_BLK(u4_blk_id) ((u4_blk_id) > 3)
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#define IND2SUB_CHROMA_MB(u4_blk_id, i4_offset_x, i4_offset_y) \
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{ \
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i4_offset_x = ((u4_blk_id & 0x1) << 3) + IS_V_BLK(u4_blk_id); \
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i4_offset_y = (u4_blk_id & 0x2) << 1; \
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}
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/* Typedefs */
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/*****************************************************************************/
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/* Function Declarations */
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/*****************************************************************************/
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extern FT_CORE_CODING isvce_code_luma_intra_macroblock_16x16;
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extern FT_CORE_CODING isvce_code_luma_intra_macroblock_4x4;
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extern FT_CORE_CODING isvce_code_luma_intra_macroblock_4x4_rdopt_on;
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extern FT_CORE_CODING isvce_code_chroma_intra_macroblock_8x8;
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extern FT_CORE_CODING isvce_code_luma_inter_macroblock_16x16;
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extern FT_CORE_CODING isvce_code_chroma_inter_macroblock_8x8;
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#endif
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