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armv8: Remove unnecessary sign extensions am: 6958350a65

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am: 4c5e34c5d2

Change-Id: Ib14ec825a174cd06150ba1e2c465bd3beda74c03
This commit is contained in:
Martin Storsjo 2016-10-14 23:57:01 +00:00 • committed by android-build-merger
commit e57c55f476
6 changed files with 50 additions and 160 deletions
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12
common/armv8/ih264_intra_pred_chroma_av8.s
View file

@ -461,18 +461,14 @@ ih264_intra_pred_chroma_8x8_mode_plane_av8:
rshrn v13.4h, v26.4s, #6
rshrn v14.4h, v28.4s, #6
ldrb w6, [x0], #1
sxtw x6, w6
add x10, x0, #31
ldrb w8, [x0], #1
sxtw x8, w8
ldrb w7, [x10], #1
sxtw x7, w7
ldrb w9, [x10], #1
sxtw x9, w9
add x6, x6, x7
add x8, x8, x9
lsl x6, x6, #4
lsl x8, x8, #4
add w6, w6, w7
add w8, w8, w9
lsl w6, w6, #4
lsl w8, w8, #4
dup v0.8h, w6
dup v2.8h, w8
dup v4.8h, v12.h[0]

67
common/armv8/ih264_intra_pred_luma_16x16_av8.s
View file

@ -448,72 +448,55 @@ ih264_intra_pred_luma_16x16_mode_plane_av8:
neg x14, x20
addp v0.8h, v0.8h, v1.8h
ldrb w8, [x7], #-1
sxtw x8, w8
ldrb w9, [x0], #1
sxtw x9, w9
saddlp v0.2s, v0.4h
sub x12, x8, x9
sub w12, w8, w9
ldrb w8, [x7], #-1
sxtw x8, w8
saddlp v0.1d, v0.2s
ldrb w9, [x0], #1
sxtw x9, w9
sub x8, x8, x9
sub w8, w8, w9
shl v2.2s, v0.2s, #2
add x12, x12, x8, lsl #1
add w12, w12, w8, lsl #1
add v0.2s, v0.2s , v2.2s
ldrb w8, [x7], #-1
sxtw x8, w8
ldrb w9, [x0], #1
sxtw x9, w9
srshr v0.2s, v0.2s, #6 // i_b = D0[0]
sub x8, x8, x9
sub w8, w8, w9
ldrb w5, [x7], #-1
sxtw x5, w5
add x8, x8, x8, lsl #1
add w8, w8, w8, lsl #1
dup v4.8h, v0.h[0]
add x12, x12, x8
add w12, w12, w8
ldrb w9, [x0], #1
sxtw x9, w9
mul v0.8h, v4.8h , v16.8h
sub x5, x5, x9
sub w5, w5, w9
mul v2.8h, v4.8h , v18.8h
add x12, x12, x5, lsl #2
add w12, w12, w5, lsl #2
ldrb w8, [x7], #-1
sxtw x8, w8
ldrb w9, [x0], #1
sxtw x9, w9
sub x8, x8, x9
sub w8, w8, w9
ldrb w5, [x7], #-1
sxtw x5, w5
add x8, x8, x8, lsl #2
add w8, w8, w8, lsl #2
ldrb w6, [x0], #1
sxtw x6, w6
add x12, x12, x8
add w12, w12, w8
ldrb w8, [x7], #-1
sxtw x8, w8
ldrb w9, [x0], #1
sxtw x9, w9
sub x5, x5, x6
sub x8, x8, x9
add x5, x5, x5, lsl #1
sub x20, x8, x8, lsl #3
neg x8, x20
add x12, x12, x5, lsl #1
sub w5, w5, w6
sub w8, w8, w9
add w5, w5, w5, lsl #1
sub w20, w8, w8, lsl #3
neg w8, w20
add w12, w12, w5, lsl #1
ldrb w5, [x7], #-1
sxtw x5, w5
ldrb w6, [x10] //top_left
sxtw x6, w6
add x12, x12, x8
sub x9, x5, x6
add w12, w12, w8
sub w9, w5, w6
ldrb w6, [x1, #7]
sxtw x6, w6
add x12, x12, x9, lsl #3 // i_c = x12
add x8, x5, x6
add x12, x12, x12, lsl #2
lsl x8, x8, #4 // i_a = x8
add x12, x12, #0x20
lsr x12, x12, #6
add w12, w12, w9, lsl #3 // i_c = w12
add w8, w5, w6
add w12, w12, w12, lsl #2
lsl w8, w8, #4 // i_a = w8
add w12, w12, #0x20
lsr w12, w12, #6
shl v28.8h, v4.8h, #3
dup v6.8h, w12
dup v30.8h, w8

41
common/armv8/ih264_intra_pred_luma_4x4_av8.s
View file

@ -271,34 +271,26 @@ ih264_intra_pred_luma_4x4_mode_dc_av8:
add x10, x0, #3
mov x2, #-1
ldrb w5, [x10], #-1
sxtw x5, w5
ldrb w6, [x10], #-1
sxtw x6, w6
ldrb w7, [x10], #-1
sxtw x7, w7
add x5, x5, x6
add w5, w5, w6
ldrb w8, [x10], #-1
sxtw x8, w8
add x5, x5, x7
add w5, w5, w7
ands w11, w4, #0x04 // CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
add x5, x5, x8
add w5, w5, w8
beq left_available
add x10, x0, #5
// BOTH LEFT AND TOP AVAILABLE
ldrb w6, [x10], #1
sxtw x6, w6
ldrb w7, [x10], #1
sxtw x7, w7
add x5, x5, x6
add w5, w5, w6
ldrb w8, [x10], #1
sxtw x8, w8
add x5, x5, x7
add w5, w5, w7
ldrb w9, [x10], #1
sxtw x9, w9
add x5, x5, x8
add x5, x5, x9
add x5, x5, #4
lsr x5, x5, #3
add w5, w5, w8
add w5, w5, w9
add w5, w5, #4
lsr w5, w5, #3
dup v0.8b, w5
st1 {v0.s}[0], [x1], x3
st1 {v0.s}[0], [x1], x3
@ -312,18 +304,14 @@ top_available: // ONLT TOP AVAILABLE
add x10, x0, #5
ldrb w6, [x10], #1
sxtw x6, w6
ldrb w7, [x10], #1
sxtw x7, w7
ldrb w8, [x10], #1
sxtw x8, w8
add x5, x6, x7
add w5, w6, w7
ldrb w9, [x10], #1
sxtw x9, w9
add x5, x5, x8
add x5, x5, x9
add x5, x5, #2
lsr x5, x5, #2
add w5, w5, w8
add w5, w5, w9
add w5, w5, #2
lsr w5, w5, #2
dup v0.8b, w5
st1 {v0.s}[0], [x1], x3
st1 {v0.s}[0], [x1], x3
@ -848,7 +836,6 @@ ih264_intra_pred_luma_4x4_mode_horz_u_av8:
mov x10, x0
ld1 {v0.8b}, [x0]
ldrb w9, [x0], #1
sxtw x9, w9
ext v1.8b, v0.8b , v0.8b , #1
ld1 {v0.b}[7], [x10]
ext v2.8b, v1.8b , v1.8b , #1

30
common/armv8/ih264_intra_pred_luma_8x8_av8.s
View file

@ -199,34 +199,26 @@ ih264_intra_pred_luma_8x8_mode_horz_av8:
add x0, x0, #7
ldrb w5, [x0], #-1
sxtw x5, w5
ldrb w6, [x0], #-1
sxtw x6, w6
dup v0.8b, w5
st1 {v0.8b}, [x1], x3
ldrb w7, [x0], #-1
sxtw x7, w7
dup v1.8b, w6
st1 {v1.8b}, [x1], x3
dup v2.8b, w7
ldrb w8, [x0], #-1
sxtw x8, w8
dup v3.8b, w8
st1 {v2.8b}, [x1], x3
ldrb w5, [x0], #-1
sxtw x5, w5
st1 {v3.8b}, [x1], x3
dup v0.8b, w5
ldrb w6, [x0], #-1
sxtw x6, w6
st1 {v0.8b}, [x1], x3
ldrb w7, [x0], #-1
sxtw x7, w7
dup v1.8b, w6
dup v2.8b, w7
st1 {v1.8b}, [x1], x3
ldrb w8, [x0], #-1
sxtw x8, w8
dup v3.8b, w8
st1 {v2.8b}, [x1], x3
st1 {v3.8b}, [x1], x3
@ -308,29 +300,21 @@ ih264_intra_pred_luma_8x8_mode_dc_av8:
add x10, x0, #7
mov x2, #-1
ldrb w5, [x10], -1
sxtw x5, w5
ldrb w6, [x10], -1
sxtw x6, w6
ldrb w7, [x10], -1
sxtw x7, w7
add x5, x5, x6
add w5, w5, w6
ldrb w8, [x10], -1
sxtw x8, w8
add x5, x5, x7
add w5, w5, w7
ldrb w6, [x10], -1
sxtw x6, w6
add x5, x5, x8
add w5, w5, w8
ldrb w7, [x10], -1
sxtw x7, w7
add x5, x5, x6
add w5, w5, w6
ldrb w8, [x10], -1
sxtw x8, w8
add x5, x5, x7
add w5, w5, w7
ands w11, w4, #0x04 // CHECKING IF TOP_AVAILABLE ELSE BRANCHING TO ONLY LEFT AVAILABLE
add x5, x5, x8
add w5, w5, w8
ldrb w6, [x10], -1
sxtw x6, w6
add x5, x5, x6
add w5, w5, w6
beq left_available
add x10, x0, #9
// BOTH LEFT AND TOP AVAILABLE

4
common/armv8/ih264_mem_fns_neon_av8.s
View file

@ -127,9 +127,7 @@ arm_memcpy:
loop_arm_memcpy:
ldrb w3, [x1], #1
sxtw x3, w3
strb w3, [x0], #1
sxtw x3, w3
subs w2, w2, #1
bne loop_arm_memcpy
ret
@ -192,7 +190,6 @@ arm_memset:
loop_arm_memset:
strb w1, [x0], #1
sxtw x1, w1
subs w2, w2, #1
bne loop_arm_memset
ret
@ -262,7 +259,6 @@ arm_memset_16bit:
loop_arm_memset_16bit:
strh w1, [x0], #2
sxtw x1, w1
subs w2, w2, #1
bne loop_arm_memset_16bit
ret

56
common/armv8/ih264_padding_neon_av8.s
View file

@ -185,39 +185,31 @@ ih264_pad_left_luma_av8:
loop_16: // /*hard coded for width=16 ,height =8,16*/
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], x1 // 16 bytes store
dup v2.16b, w9
st1 {v2.16b}, [x4], x1 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
dup v4.16b, w10
dup v6.16b, w11
st1 {v4.16b}, [x4], x1 // 16 bytes store
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
st1 {v6.16b}, [x4], x1 // 16 bytes store
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], x1 // 16 bytes store
dup v2.16b, w9
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], x1 // 16 bytes store
dup v4.16b, w10
dup v6.16b, w11
@ -230,14 +222,11 @@ loop_16: // /*hard coded for width=16 ,height =
loop_32: // /*hard coded for width=32 ,height =8,16*/
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.16b, w9
st1 {v0.16b}, [x4], x6
@ -246,28 +235,23 @@ loop_32: // /*hard coded for width=32 ,height =8
st1 {v2.16b}, [x4], x6 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v4.16b}, [x4], #16 // 16 bytes store
dup v6.16b, w11
st1 {v4.16b}, [x4], x6 // 16 bytes store
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
st1 {v6.16b}, [x4], #16 // 16 bytes store
dup v0.16b, w8
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
st1 {v6.16b}, [x4], x6 // 16 bytes store
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.16b, w9
st1 {v0.16b}, [x4], x6 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.16b, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -359,20 +343,16 @@ ih264_pad_left_chroma_av8:
loop_32_l_c: // /*hard coded for width=32 ,height =4,8,12*/
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.8h, w8
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6 // 16 bytes store
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.8h, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -388,20 +368,16 @@ loop_32_l_c: // /*hard coded for width=32 ,height =
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.8h, w8
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.8h, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -417,20 +393,16 @@ loop_32_l_c: // /*hard coded for width=32 ,height =
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.8h, w8
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.8h, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -529,39 +501,31 @@ ih264_pad_right_luma_av8:
loop_16_r: // /*hard coded for width=16 ,height =8,16*/
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], x1 // 16 bytes store
dup v2.16b, w9
st1 {v2.16b}, [x4], x1 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
dup v4.16b, w10
dup v6.16b, w11
st1 {v4.16b}, [x4], x1 // 16 bytes store
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
st1 {v6.16b}, [x4], x1 // 16 bytes store
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], x1 // 16 bytes store
dup v2.16b, w9
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], x1 // 16 bytes store
dup v4.16b, w10
dup v6.16b, w11
@ -574,14 +538,11 @@ loop_16_r: // /*hard coded for width=16 ,height =8,16*/
loop_32_r: // /*hard coded for width=32 ,height =8,16*/
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.16b, w9
st1 {v0.16b}, [x4], x6
@ -590,28 +551,23 @@ loop_32_r: // /*hard coded for width=32 ,height =
st1 {v2.16b}, [x4], x6 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v4.16b}, [x4], #16 // 16 bytes store
dup v6.16b, w11
st1 {v4.16b}, [x4], x6 // 16 bytes store
ldrb w8, [x0]
add x0, x0, x1
sxtw x8, w8
st1 {v6.16b}, [x4], #16 // 16 bytes store
ldrb w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.16b, w8
st1 {v6.16b}, [x4], x6 // 16 bytes store
ldrb w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.16b, w9
st1 {v0.16b}, [x4], x6 // 16 bytes store
ldrb w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.16b, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -701,14 +657,11 @@ ih264_pad_right_chroma_av8:
loop_32_r_c: // /*hard coded for width=32 ,height =8,4*/
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
dup v0.8h, w8
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6
@ -718,7 +671,6 @@ loop_32_r_c: // /*hard coded for width=32 ,height =8,4*/
subs w2, w2, #4
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v4.16b}, [x4], #16 // 16 bytes store
dup v6.8h, w11
st1 {v4.16b}, [x4], x6 // 16 bytes store
@ -729,20 +681,16 @@ loop_32_r_c: // /*hard coded for width=32 ,height =8,4*/
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
dup v0.8h, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6 // 16 bytes store
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.8h, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store
@ -757,20 +705,16 @@ loop_32_r_c: // /*hard coded for width=32 ,height =8,4*/
bne loop_32_r_c
ldrh w8, [x0]
add x0, x0, x1
sxtw x8, w8
dup v0.8h, w8
ldrh w9, [x0]
add x0, x0, x1
sxtw x9, w9
ldrh w10, [x0]
add x0, x0, x1
sxtw x10, w10
st1 {v0.16b}, [x4], #16 // 16 bytes store
dup v2.8h, w9
st1 {v0.16b}, [x4], x6 // 16 bytes store
ldrh w11, [x0]
add x0, x0, x1
sxtw x11, w11
st1 {v2.16b}, [x4], #16 // 16 bytes store
dup v4.8h, w10
st1 {v2.16b}, [x4], x6 // 16 bytes store