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Shreesh Adiga 26f2f03e0d swscale/x86/rgb2rgb: optimize AVX2 version of uyvytoyuv422 
Currently the AVX2 version of uyvytoyuv422 in the SIMD loop does the following:
4 vinsertq to have interleaving of the vector lanes during load from memory.
4 vperm2i128 inside 4 RSHIFT_COPY calls to achieve the desired layout.

This patch replaces the above 8 instructions with 2 vpermq and
2 vpermd with a vector register similar to AVX512ICL version.

Observed the following numbers on various microarchitectures:

On AMD Zen3 laptop:
Before:
uyvytoyuv422_c:                                      51979.7 ( 1.00x)
uyvytoyuv422_sse2:                                    5410.5 ( 9.61x)
uyvytoyuv422_avx:                                     4642.7 (11.20x)
uyvytoyuv422_avx2:                                    4249.0 (12.23x)

After:
uyvytoyuv422_c:                                      51659.8 ( 1.00x)
uyvytoyuv422_sse2:                                    5420.8 ( 9.53x)
uyvytoyuv422_avx:                                     4651.2 (11.11x)
uyvytoyuv422_avx2:                                    3953.8 (13.07x)

On Intel Macbook Pro 2019:
Before:
uyvytoyuv422_c:                                     185014.4 ( 1.00x)
uyvytoyuv422_sse2:                                   22800.4 ( 8.11x)
uyvytoyuv422_avx:                                    19796.9 ( 9.35x)
uyvytoyuv422_avx2:                                   13141.9 (14.08x)

After:
uyvytoyuv422_c:                                     185093.4 ( 1.00x)
uyvytoyuv422_sse2:                                   22795.4 ( 8.12x)
uyvytoyuv422_avx:                                    19791.9 ( 9.35x)
uyvytoyuv422_avx2:                                   12043.1 (15.37x)

On AMD Zen4 desktop:
Before:
uyvytoyuv422_c:                                      29105.0 ( 1.00x)
uyvytoyuv422_sse2:                                    3888.0 ( 7.49x)
uyvytoyuv422_avx:                                     3374.2 ( 8.63x)
uyvytoyuv422_avx2:                                    2649.8 (10.98x)
uyvytoyuv422_avx512icl:                               1615.0 (18.02x)

After:
uyvytoyuv422_c:                                      29093.4 ( 1.00x)
uyvytoyuv422_sse2:                                    3874.4 ( 7.51x)
uyvytoyuv422_avx:                                     3371.6 ( 8.63x)
uyvytoyuv422_avx2:                                    2174.6 (13.38x)
uyvytoyuv422_avx512icl:                               1625.1 (17.90x)

Signed-off-by: Shreesh Adiga <16567adigashreesh@gmail.com>
2025-03-23 15:25:48 +00:00
..
hscale_fast_bilinear_simd.c swscale: rename SwsContext to SwsInternal 2024-10-24 22:50:00 +02:00
input.asm swscale/x86/rgb2rgb: fix deinterleaveBytes for unaligned dst pointers 2024-09-06 23:05:01 +02:00
Makefile swscale/x86: add sse2 and avx2 {lum,chr}ConvertRange 2024-06-16 00:35:51 +02:00
output.asm swscale: add ICC intent enum and option 2024-12-23 12:33:43 +01:00
range_convert.asm swscale/x86: add sse4 and avx2 {lum,chr}ConvertRange16 2024-12-05 21:10:29 +01:00
rgb2rgb.c swscale/x86/rgb2rgb: add AVX512ICL version of uyvytoyuv422 2025-02-18 12:43:57 -03:00
rgb_2_rgb.asm swscale/x86/rgb2rgb: optimize AVX2 version of uyvytoyuv422 2025-03-23 15:25:48 +00:00
scale.asm swscale: rename SwsContext to SwsInternal 2024-10-24 22:50:00 +02:00
scale_avx2.asm swscale: rename SwsContext to SwsInternal 2024-10-24 22:50:00 +02:00
swscale.c swscale/x86/swscale: Make M24 variables static 2025-02-02 17:03:13 +01:00
swscale_template.c swscale/x86/swscale: Make M24 variables static 2025-02-02 17:03:13 +01:00
w64xmmtest.c swscale: rename SwsContext to SwsInternal 2024-10-24 22:50:00 +02:00
yuv2rgb.c swscale/internal: group user-facing options together 2024-11-21 12:49:56 +01:00
yuv2yuvX.asm x86: replace explicit REP_RETs with RETs 2023-02-01 04:23:55 +01:00
yuv_2_rgb.asm swscale/x86/yuv2rgb: add ssse3 yuv42{0,2}p -> gbrp unscaled colorspace converters 2024-08-18 22:26:14 +02:00