Rémi Denis-Courmont f59a767ccd lavu/riscv: helper macro for VTYPE encoding ... On most cases, the vector type (VTYPE) for the RISC-V Vector extension is supplied as an immediate value, with either of the VSETVLI or VSETIVLI instructions. There is however a third instruction VSETVL which takes the vector type from a general purpose register. That is so the type can be selected at run-time. This introduces a macro to load a (valid) vector type into a register. The syntax follows that of VSETVLI and VSETIVLI, with element size, group multiplier, then tail and mask policies.		2022-10-10 02:22:12 +02:00
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asm.S	lavu/riscv: helper macro for VTYPE encoding	2022-10-10 02:22:12 +02:00
bswap.h
cpu.c	lavu/riscv: CPU flag for the Zbb extension	2022-10-05 08:26:19 +02:00
cpu.h	lavu/riscv: helper to read the vector length	2022-09-28 11:43:17 +02:00
fixed_dsp_init.c	lavu/fixeddsp: RISC-V V butterflies_fixed	2022-09-27 13:19:52 +02:00
fixed_dsp_rvv.S	riscv: remove unnecessary #include's	2022-10-05 06:54:56 +02:00
float_dsp_init.c	lavu/floatdsp: RISC-V V scalarproduct_float	2022-09-27 13:19:52 +02:00
float_dsp_rvv.S	riscv: remove unnecessary #include's	2022-10-05 06:54:56 +02:00
intmath.h	lavu/riscv: fix off-by-one in bit-magnitude clip	2022-09-15 18:11:12 -03:00
Makefile	lavu/fixeddsp: RISC-V V butterflies_fixed	2022-09-27 13:19:52 +02:00
timer.h