From 5afe734b6dc9404f4e53ef02507646d56a669456 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Tue, 7 May 2024 21:08:43 +0300
Subject: [PATCH] lavu/riscv: remove bespoke assembler for MIN

This is no longer necessary as Zbb is now always explicitly required.
---
 libavutil/riscv/asm.S | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S
index 9d76ab5617..14be5055f5 100644
--- a/libavutil/riscv/asm.S
+++ b/libavutil/riscv/asm.S
@@ -95,11 +95,6 @@
         shnadd  3, \rd, \rs1, \rs2
         .endm
 #endif
-#if !defined (__riscv_zbb)
-        .macro  min rd, rs1, rs2
-        .insn r OP, 4, 5, \rd, \rs1, \rs2
-        .endm
-#endif
 
         /* Convenience macro to load a Vector type (vtype) as immediate */
         .macro  lvtypei rd, e, m=m1, tp=tu, mp=mu