61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* OneNAND controller template */
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#include "../onenand.h"
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#include "controller.h"
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#include <stdint.h>
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#include "dcc/dn_dcc_proto.h"
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void OneNAND_Pre_Initialize(DCCMemory *mem, uint32_t offset, uint32_t page_size) {
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// Initialize routines
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mem->base_offset = offset;
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if (page_size != 0x800 && page_size != 0x1000) {
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page_size = 0x800;
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}
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mem->page_size = page_size;
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OneNAND_Ctrl_Reg_Write(mem, O1N_REG_SYS_CFG1, 0x40c0, 0);
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OneNAND_Ctrl_Reg_Write(mem, O1N_REG_START_ADDRESS1, 0x0, 0);
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OneNAND_Ctrl_Reg_Write(mem, O1N_REG_START_ADDRESS2, 0x0, 0);
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OneNAND_Ctrl_Reg_Write(mem, O1N_REG_INTERRUPT, 0x0, 0);
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OneNAND_Ctrl_Reg_Write(mem, O1N_REG_COMMAND, O1N_CMD_HOT_RESET, 1);
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}
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int OneNAND_Ctrl_Wait_Ready(DCCMemory *mem, uint16_t flag) {
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// Busy assert routines
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int timeout = 0x10000;
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do {
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wdog_reset();
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if (timeout == 0) return 0;
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timeout--;
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} while ((OneNAND_Ctrl_Reg_Read(mem, O1N_REG_INTERRUPT) & flag) != flag);
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return 1;
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}
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void OneNAND_Ctrl_Reg_Write(DCCMemory *mem, uint16_t reg, uint16_t data, uint8_t wait_interrupt) {
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// Write register routines
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WRITE_U16(mem->base_offset + (reg << 1), data);
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}
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uint16_t OneNAND_Ctrl_Reg_Read(DCCMemory *mem, uint16_t reg) {
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// Read register routines
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return READ_U16(mem->base_offset + (reg << 1));
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}
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void OneNAND_Ctrl_Reg_Write_Queue(DCCMemory *mem, uint16_t reg, uint16_t data) {
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OneNAND_Ctrl_Reg_Write(mem, reg, data, 0);
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}
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int OneNAND_Ctrl_Execute_Queue(uint8_t wait_interrupt) {
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return 1;
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}
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void OneNAND_Ctrl_Get_Data(DCCMemory *mem, uint8_t *page_buf, uint8_t *spare_buf, uint32_t page_size, uint32_t spare_size) {
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memcpy(page_buf, (uint8_t *)(mem->base_offset + (O1N_DATARAM << 1)), page_size);
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memcpy(spare_buf, (uint8_t *)(mem->base_offset + (O1N_SPARERAM << 1)), spare_size);
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}
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