253 lines
6.5 KiB
ArmAsm
253 lines
6.5 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-3-Clause */
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/****************************************************************************
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* Copyright (c) 2006 by Michael Fischer. All rights reserved.
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****************************************************************************
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*
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* History:
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*
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* 18.12.06 mifi First Version
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* The hardware initialization is based on the startup file
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* crtat91sam7x256_rom.S from NutOS 4.2.1.
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* Therefore partial copyright by egnite Software GmbH.
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****************************************************************************/
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/*
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* Some defines for the program status registers
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*/
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ARM_MODE_USER = 0x10 /* Normal User Mode */
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ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
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ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
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ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
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ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
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ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
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ARM_MODE_SYS = 0x1F /* System Running in Privileged Operating Mode */
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ARM_MODE_MASK = 0x1F
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I_BIT = 0x80 /* disable IRQ when I bit is set */
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F_BIT = 0x40 /* disable IRQ when I bit is set */
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/****************************************************************************/
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/* Vector table and reset entry */
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/****************************************************************************/
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.section .init, "ax"
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.code 32
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_vectors:
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b ResetHandler /* Reset */
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b UndefHandler /* Undefined instruction */
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b SWIHandler /* Software interrupt */
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b PAbortHandler /* Prefetch abort */
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b DAbortHandler /* Data abort */
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b CrashHandler /* Reserved */
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b IRQHandler /* IRQ interrupt */
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b FIQHandler /* FIQ interrupt */
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.ltorg
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.global ResetHandler
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.global ExitFunction
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.global __assert_func
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#if USE_BREAKPOINTS
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.global DN_Packet_DCC_WaitForBP
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.global DCC_PKT_RW_DATA
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.global DCC_PKT_RW_SIZE
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#endif
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#ifdef USE_PIC
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.extern pic_relocate
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#endif
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.extern dcc_main
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.extern __stack_und_end
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/* Variables */
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StartAddress: .word 0xAAAAAAAA
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NoAutoSize: .word 0x0
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PageSize: .word 0xAAAAAAAA
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/* Loader via H/W BP polling */
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DCC_PKT_RW_SIZE: .word 0x0
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DCC_PKT_RW_DATA: .word 0x0
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DCC_PKT_HW_BP: .word DN_Packet_DCC_WaitForBP
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DCC_UNKNOWN_VALUE: .word 0x0 /* Used in MSM6550 loader when set, disables write operations to DCC */
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/* Crash handlers */
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UndefHandler:
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SWIHandler:
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PAbortHandler:
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DAbortHandler:
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IRQHandler:
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FIQHandler:
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CrashHandler:
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__assert_func: /* the original code prints assertion failed then aborts */
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b CrashHandler
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.word CrashHandler
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/* DCC info */
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.ascii "DNDL"
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.short 0xfffe
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#ifdef USE_PIC
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.short 1
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#else
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.short 0
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#endif
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.word _vectors
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.word __bss_start
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.word __heap_start - _vectors
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.word LOADER_MIN_RAM
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.asciz "A:DumpNow DCC Loader. (c) 2026 Wrapper.;Compile flags: " ADEFS ";Compile Date: " __DATE__
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.align
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/****************************************************************************/
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/* Reset handler */
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/****************************************************************************/
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ResetHandler:
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/*
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* Setup a stack for each mode
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*/
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
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#if USE_ICACHE \
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&& (( defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) ) \
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|| ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) \
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|| ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_7R__) ) \
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|| ( defined(CPU_XSCALE) ))
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mrc p15, 0, r0, cr1, cr0, 0
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orr r0, #0x1000
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mcr p15, 0, r0, cr1, cr0, 0
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#endif
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/* Needed to flush DCC read buffer */
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#if \
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( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) \
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|| ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_7R__) )
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mrc p14, 0, r0, cr0, cr5, 0
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#elif defined(CPU_XSCALE)
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mrc p14, 0, r0, cr9, cr0, 0
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#else
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mrc p14, 0, r0, cr1, cr0, 0
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#endif
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/* 01 - Initialize stack section */
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#ifdef USE_PIC
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mov r0, #0
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adr r0, _vectors
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#endif
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ldr sp, =__stack_svc_end
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#ifdef USE_PIC
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add sp, r0
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#endif
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bl plat_init
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/* 02 - Reset memory */
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#ifdef USE_PIC
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mov r0, #0
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adr r0, _vectors
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#endif
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/*
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* Clear .bss section
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*/
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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mov r3, #0
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#ifdef USE_PIC
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add r1, r0
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add r2, r0
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#endif
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bss_clear_loop:
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cmp r1, r2
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strne r3, [r1], #+4
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bne bss_clear_loop
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/* 03 - Code initialize */
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#ifdef USE_PIC
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mov r0, #0
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adr r0, _vectors
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/* Setup PIC */
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ldr r1, =_reloc_start
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ldr r2, =_reloc_end
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add r1, r0
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add r2, r0
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ldr r3, =edata
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bl pic_relocate
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/* Setup GOT */
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ldr r9, =_sgot
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add r9, r0
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#endif
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/* 04 - Jump to Main */
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mov r0, #0
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adr r0, StartAddress
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ldr r0, [r0]
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mov r1, #0
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adr r1, PageSize
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ldr r1, [r1]
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mov r2, #0 /* No arguments */
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mov r3, #0 /* No arguments */
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b dcc_main
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ExitFunction:
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nop
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nop
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nop
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b ExitFunction
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/* Breakpoint loader routines */
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#if USE_BREAKPOINTS
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DN_Packet_DCC_WaitForBP:
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b DN_Packet_DCC_WaitForBP
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mov r0, #0
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adr r0, DCC_PKT_RW_DATA
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ldr r0, [r0]
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bx lr
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#else
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DN_Packet_DCC_WaitForBP:
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b DN_Packet_DCC_WaitForBP
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bx lr
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#endif
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/* libc functions */
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.global memset
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memset:
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mov r3, r0
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memset.loop:
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subs r2, r2, #1
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bmi memset.ret
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strb r1, [r0], #1
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b memset.loop
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memset.ret:
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mov r0, r3
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bx lr
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.global strlen
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strlen:
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mov r2, r0
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strlen.loop:
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ldrb r1, [r0], #1
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tst r1, r1
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bne strlen.loop
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sub r0, r0, r2
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sub r0, r0, #1
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bx lr
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/* End */
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.weak ExitFunction
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.weak UndefHandler, PAbortHandler, DAbortHandler
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.weak IRQHandler, FIQHandler
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.ltorg
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/*** EOF ***/
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