diff --git a/dcc/plat.h b/dcc/plat.h
index f7c5e98..15923e7 100644
--- a/dcc/plat.h
+++ b/dcc/plat.h
@@ -45,4 +45,11 @@ extern void *PLAT_MEMCPY(void *dest, const void *src, size_t n);
 #define PLAT_MEMCPY memcpy
 #define INT_MEMCPY memcpy
 #define PLAT_SNPRINTF lwprintf_snprintf
+
+#if DEBUG_PORT
+#define PLAT_DBG_LOG lwprintf_printf
+#else
+#define PLAT_DBG_LOG(fmt, ...)
+#endif
+
 #endif
\ No newline at end of file
diff --git a/main.c b/main.c
index 401dfe6..ad66d1a 100644
--- a/main.c
+++ b/main.c
@@ -54,6 +54,14 @@ static inline uint8_t dcc_send_data(uint8_t *data, uint32_t size, uint8_t algo)
     return 1;
 }
 
+#if DEBUG_PORT
+static int DN_DebugPort_Out(int ch, lwprintf_t* lwp) {
+    if (ch != 0x00)
+        WRITE_U32(0x44444440, ch);
+    return ch;
+}
+#endif
+
 // dcc code
 void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
     DCCMemory dev_mem[16] = { 0 };
@@ -63,12 +71,21 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
     uint32_t temp_ext_mem;
     DCC_RETURN res;
 
+    /* 00 - Init debug stuff */
+#if DEBUG_PORT
+    lwprintf_init(DN_DebugPort_Out);
+#endif
+
     /* 01 - Probe flash devices */
+    PLAT_DBG_LOG("[DUMPNOW_DCC]: Begin initializing memory devices\n");
+
     for (int i = 0; i < 16; i++) {
         if (!devices[i].driver) break; // Break when reaching the end of list
 
         /* Probe device */
         res = devices[i].driver->initialize(&dev_mem[i], devices[i].base_offset, PageSize);
+        PLAT_DBG_LOG("[DUMPNOW_DCC]: Memory device %d initialization returned 0x%02x\n", i + 1, res);
+
         if (res != DCC_OK) 
             dev_mem[i].type = MEMTYPE_NONE;
 
@@ -145,6 +162,8 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
     uint32_t readDestSize;
 
     /* 03 - The loop */
+    PLAT_DBG_LOG("[DUMPNOW_DCC]: Ready to accept commands\n");
+
     while (1) {
         wdog_reset();
         uint32_t cmd = DN_Packet_DCC_Read();
diff --git a/makefile b/makefile
index 57f18a3..cde3b2c 100644
--- a/makefile
+++ b/makefile
@@ -126,6 +126,10 @@ DADEFS += -DUSE_PIC
 ADD_DEPS += dcc/pic.c
 endif
 
+ifeq ($(DEBUG_LOG), 1)
+DDEFS += -DDEBUG_PORT=1
+endif
+
 # List C source files here
 SRC = main.c dcc/memory.c dcc/dn_dcc_proto.c dcc/bitutils.c dcc/lwprintf.c plat/$(PLATFORM).c devices/$(LOADER_DEVICES).c $(DEVICES) $(CONTROLLERS) $(ADD_DEPS)
 
@@ -245,6 +249,7 @@ endif
 	$(info $(NULL)  PIC=1 = Use PIC code)
 	$(info $(NULL)  LOADER_LOAD_START=(LOAD_OFFSET_IN_HEX) = With LDSCRIPT unset, set loader start offset)
 	$(info $(NULL)  LOADER_LOAD_SIZE_KB=(LOAD_SIZE_IN_KB) = With LDSCRIPT unset, set RAM size for the loader)
+	$(info $(NULL)  DEBUG_LOG=1 = Enable debug logs (only useful during development))
 	$(info Flash devices:)
 	$(info $(NULL)  CFI=1 = Enable CFI interface)
 	$(info $(NULL)  NAND_CONTROLLER=(name) = Enable NAND controller)
diff --git a/tools/emulator/emulator.py b/tools/emulator/emulator.py
index 01355d1..63c9dc0 100644
--- a/tools/emulator/emulator.py
+++ b/tools/emulator/emulator.py
@@ -11,6 +11,7 @@ from sys import stderr
 from prompt_toolkit import PromptSession
 import shlex
 from array import array
+from flash.shared import DebugPort
 
 class IntorHex(int):
     def __new__(cls, value: str | int | bytearray | bytes):
@@ -37,6 +38,7 @@ def main(
     init_flash: str = ""
 ) -> int:
     emu = DynemuEmulator(open(loader, "rb").read(), loader_offset & ~3, loader_size, bool(loader_offset & 1))
+    emu.mount_flash_chip(DebugPort(), 0x44444440, 0x10)
 
     if len(init_flash) > 0:
         mod = import_module(f"init.{init_flash}")
diff --git a/tools/emulator/flash/shared.py b/tools/emulator/flash/shared.py
index 16f796a..36147ed 100644
--- a/tools/emulator/flash/shared.py
+++ b/tools/emulator/flash/shared.py
@@ -16,6 +16,14 @@ class OpenBus(FlashChip):
     def write(self, vaddr: int, value: int, access: int) -> None:
         pass
 
+    @override
+    def read(self, vaddr: int, access: int) -> int:
+        return vaddr & ((2 ** (access * 8)) - 1)  # pyright: ignore[reportAny]
+class DebugPort(FlashChip):
+    @override
+    def write(self, vaddr: int, value: int, access: int) -> None:
+        print(chr(value), end="")
+
     @override
     def read(self, vaddr: int, access: int) -> int:
         return vaddr & ((2 ** (access * 8)) - 1)  # pyright: ignore[reportAny]
\ No newline at end of file