redone make, init, update CFI
This commit is contained in:
wrapper
parent
645678b438
commit
ac2f32ba7b
11 changed files with 208 additions and 120 deletions
3
.gitignore
vendored
3
.gitignore
vendored
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@ -12,4 +12,5 @@ compress_test.bat
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*.cmm
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*.bak
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build/*.has
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dcc_test_*
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dcc_test_*
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build_script/
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@ -101,5 +101,10 @@ SECTIONS
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PROVIDE (__heap_start = .);
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} > ram
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.heap : {
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__heap_end = LENGTH(ram);
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__heap_size = LENGTH(ram) - __heap_start;
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}
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}
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/*** EOF ***/
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91
crt.s
91
crt.s
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@ -48,8 +48,8 @@ _vectors:
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.global ResetHandler
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.global ExitFunction
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.global absolute_to_relative
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#if USE_BREAKPOINTS
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.global DN_Packet_DCC_WaitForBP
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#if USE_BREAKPOINTS
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.global DN_Packet_DCC_ResetBPP
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.global DN_Packet_DCC_Send
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#endif
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@ -57,24 +57,30 @@ _vectors:
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.extern __stack_und_end
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/* Variables */
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StartAddress: .word 0x12345678
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StartAddress: .word 0xffffffff
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unk1: .word 0x12345678
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PageSize: .word 0x12345678
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PageSize: .word 0xffffffff
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/* Loader via H/W BP polling */
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#if USE_BREAKPOINTS
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DCC_PKT_RW_SIZE: .word 0xffffffff
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DCC_PKT_RW_DATA: .word 0xffffffff
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DCC_PKT_HW_BP: .word DN_Packet_DCC_WaitForBP
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.word 0x12345678
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#endif
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.word __heap_size
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.word __stack_end
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.asciz "A:DumpNow DCC Loader. (c) 2025 Wrapper. Compile flags: " ADEFS
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.align
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/* LWMEM info */
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#if HAVE_LWMEM
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lwmem_init:
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.word __heap_start
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.word 0x00040000
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.word __heap_size
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lwmem_init_end:
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.word 0x00000000
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.word 0x00000000
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#endif
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/****************************************************************************/
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/* Reset handler */
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/****************************************************************************/
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@ -85,24 +91,6 @@ ResetHandler:
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mov r0, #0
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adr r0, _vectors
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#ifdef SETUP_STACK_OTHERS
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msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
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ldr sp, =__stack_und_end
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add sp, r0
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msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
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ldr sp, =__stack_abt_end
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add sp, r0
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
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ldr sp, =__stack_fiq_end
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add sp, r0
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
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ldr sp, =__stack_irq_end
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add sp, r0
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#endif
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
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ldr sp, =__stack_svc_end
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add sp, r0
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@ -110,7 +98,8 @@ ResetHandler:
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#if USE_ICACHE \
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&& (( defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) ) \
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|| ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) \
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|| ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_7R__) ))
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|| ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_7R__) ) \
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|| ( defined(CPU_XSCALE) ))
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mrc p15, 0, r0, cr1, cr0, 0
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orr r0, #0x1000
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mcr p15, 0, r0, cr1, cr0, 0
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@ -121,12 +110,11 @@ ResetHandler:
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mov r0, #0
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adr r0, _vectors
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#ifndef DONT_CLEAR_BSS
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/*
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* Clear .bss section
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*/
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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mov r3, #0
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add r1, r0
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@ -135,19 +123,26 @@ bss_clear_loop:
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cmp r1, r2
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strne r3, [r1], #+4
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bne bss_clear_loop
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#endif
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#if HAVE_LWMEM
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/*
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* Clear .heap section
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*/
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ldr r1, =__heap_start
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ldr r2, =__heap_end
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mov r3, #0
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add r1, r0
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add r2, r0
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heap_clear_loop:
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cmp r1, r2
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strne r3, [r1], #+4
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bne heap_clear_loop
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#endif
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/*
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* Jump to main
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*/
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#ifdef ENABLE_DCC_INTERRUPTS
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mrs r0, cpsr
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bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt (TODO: RIFF doesn't enable interrupt?) */
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msr cpsr, r0
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#endif
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#if HAVE_LWMEM
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/*
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* Setup lwmem memory manager
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@ -174,12 +169,8 @@ bss_clear_loop:
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/*
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* Start
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*/
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mov r0, #0 /* No arguments */
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mov r1, #0 /* No arguments */
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mov r2, #0 /* No arguments */
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mov r3, #0 /* No arguments */
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/* TOOD: Why is this line necessary */
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/* TODO: Why is this line necessary */
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#if \
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( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) \
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|| ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_7R__) )
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@ -199,6 +190,8 @@ bss_clear_loop:
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adr r1, PageSize
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ldr r1, [r1]
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mov r2, #0 /* No arguments */
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mov r3, #0 /* No arguments */
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b dcc_main
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@ -288,9 +281,25 @@ DN_Packet_DCC_Send:
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/* 06 - End */
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mov r0, #1
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bx lr
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#else
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DN_Packet_DCC_WaitForBP:
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b DN_Packet_DCC_WaitForBP
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bx lr
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#endif
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/* libc functions */
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.global memset
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memset:
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mov r3, r0
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memset.loop:
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subs r2, r2, #1
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bmi memset.ret
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strb r1, [r0], #1
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b memset.loop
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memset.ret:
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mov r0, r3
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bx lr
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.global strlen
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strlen:
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mov r2, r0
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@ -419,7 +419,7 @@ void DN_Packet_WriteDirectCompressed(uint8_t *src, uint32_t size) {
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}
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SIZE = outOffset - 4;
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DN_Packet_DCC_Send(outOffset >> 2);
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DN_Packet_DCC_Send((outOffset + 4) >> 2);
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DN_Packet_DCC_Send_Buffer32(MAGIC);
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DN_Packet_DCC_Send_Buffer32(SIZE);
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20
dcc/memory.c
20
dcc/memory.c
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@ -1,31 +1,21 @@
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#include <stddef.h>
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#include "dn_dcc_proto.h"
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#define MEMORY_WDOG_COUNTER 0x7f
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void *memcpy(void *dst, const void *src, size_t len)
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{
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const char *s = src;
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char *d = dst;
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while (len--) {
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if ((len & 0x3f) == 0x3f) wdog_reset();
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if ((len & MEMORY_WDOG_COUNTER) == MEMORY_WDOG_COUNTER) wdog_reset();
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*d++ = *s++;
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}
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return dst;
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}
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void *memset(void *dst, int val, size_t count)
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{
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register uint8_t *ptr = (uint8_t *)dst;
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while (count-- > 0) {
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if ((count & 0x3f) == 0x3f) wdog_reset();
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*ptr++ = val;
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}
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return dst;
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}
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void *memmove(void *dst, const void *src, size_t len)
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{
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/*
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@ -45,7 +35,7 @@ void *memmove(void *dst, const void *src, size_t len)
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const char *s = (const char *)src + len;
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char *d = (char *)dst + len;
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while (d != end) {
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if (((size_t)d & 0x3f) == 0x3f) wdog_reset();
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if (((size_t)d & MEMORY_WDOG_COUNTER) == MEMORY_WDOG_COUNTER) wdog_reset();
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*--d = *--s;
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}
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}
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@ -60,7 +50,7 @@ int memcmp(const void *s1, const void *s2, size_t len)
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unsigned char dc;
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while (len--) {
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if ((len & 0x3f) == 0x3f) wdog_reset();
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if ((len & MEMORY_WDOG_COUNTER) == MEMORY_WDOG_COUNTER) wdog_reset();
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sc = *s++;
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dc = *d++;
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if (sc - dc)
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27
dcc_emu.py
27
dcc_emu.py
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@ -7,6 +7,7 @@ from unicorn import *
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from unicorn.arm_const import *
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from capstone import *
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from capstone.arm import *
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import crcmod
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DEBUG = True
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@ -18,6 +19,7 @@ def hook_block(uc, address, size, user_data):
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status_reg = 0b0100 << 28 # By default, the DCC loader can write, but not read
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rd_reg = 0
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wr_reg = 0
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DCC_LOADER = "build/dumpnow.bin"
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# callback for tracing instructions
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def hook_code(uc: Uc, address, size, user_data):
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@ -106,7 +108,7 @@ def test_arm():
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mu.mem_map(0x14000000, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0x14000000, open("build/dumpnow.bin", "rb").read())
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mu.mem_write(0x14000000, open(DCC_LOADER, "rb").read())
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#mu.mem_write(0x00000000, open("cfi_32mb.bin", "rb").read())
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#mu.mem_write(0x00000000, b"\x01\x00\x7e\x22") # Infineon NOR
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#mu.mem_write(0x14000020, b"\x00\x00\x00\x00") # Infineon NOR
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@ -141,8 +143,8 @@ def test_arm():
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mu.mem_write(0x12000000, b"\x01\x00\x7e\x22")
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elif (address & 0x1ffff) == 0x0 and value == 0xf0:
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mu.mem_write(0x00000000, open("build/dumpnow.bin", "rb").read())
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mu.mem_write(0x12000000, open("build/dumpnow.bin", "rb").read())
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mu.mem_write(0x00000000, open(DCC_LOADER, "rb").read())
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mu.mem_write(0x12000000, open(DCC_LOADER, "rb").read())
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# mu.reg_write(0x)
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print("Write at", hex(address), size, hex(value))
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# if value == 0x98:
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@ -203,10 +205,20 @@ def _dcc_loader_read():
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while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
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iCount = _dcc_read_host()
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print("C:", hex(iCount))
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for _ in range(iCount + 1):
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crc = crcmod.mkCrcFun(0x104c11db7, 0xffffffff, False, 0)
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hashData = bytearray()
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for _ in range(iCount):
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while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
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print("H:", hex(_dcc_read_host()))
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dccRead = _dcc_read_host()
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print("H:", hex(dccRead))
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hashData += dccRead.to_bytes(4, "little")
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while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
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sum = _dcc_read_host()
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hash = crc(hashData)
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assert sum == hash, f"Checksum is invalid! 0x{sum:08x} != 0x{hash:08x}"
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if __name__ == '__main__':
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import threading
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@ -234,4 +246,5 @@ if __name__ == '__main__':
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time.sleep(4)
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print("end testing")
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print("end testing")
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@ -7,12 +7,14 @@ from unicorn import *
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from unicorn.arm_const import *
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import time
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import struct
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import crcmod
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DEBUG = True
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bp_offset = 0
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WAIT_RESPONSE = False
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data_rd = b""
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DCC_LOADER = "build/dumpnow_bp.bin"
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# callback for tracing basic blocks
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def hook_block(uc, address, size, user_data):
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@ -73,13 +75,14 @@ def test_arm():
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mu.ctl_set_exits([0])
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mu.mem_map(0x00000000, 32 * 1024 * 1024)
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mu.mem_map(0x12000000, 32 * 1024 * 1024)
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mu.mem_map(0x03000000, 2 * 1024 * 1024)
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# map 2MB memory for this emulation
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mu.mem_map(0x14000000, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0x14000000, open("build/dumpnow.bin", "rb").read())
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mu.mem_write(0x14000000, open(DCC_LOADER, "rb").read())
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bp_offset = int.from_bytes(mu.mem_read(0x14000034, 4), "little")
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#mu.mem_write(0x00000000, open("cfi_32mb.bin", "rb").read())
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#mu.mem_write(0x00000000, b"\x01\x00\x7e\x22") # Infineon NOR
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@ -106,14 +109,17 @@ def test_arm():
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def on_write(mu, access, address, size, value, data):
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if DEBUG:
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if address <= 0x14000000:
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if address == 0xaaa and value == 0x98:
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if (address & 0x1ffff) == 0xaaa and value == 0x98:
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mu.mem_write(0x00000000, open("cfi_32mb.bin", "rb").read())
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mu.mem_write(0x12000000, open("cfi_32mb.bin", "rb").read())
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elif address == 0xaaa and value == 0x90:
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elif (address & 0x1ffff) == 0xaaa and value == 0x90:
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mu.mem_write(0x00000000, b"\x01\x00\x7e\x22")
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mu.mem_write(0x12000000, b"\x01\x00\x7e\x22")
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elif address == 0x0 and value == 0xf0:
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mu.mem_write(0x00000000, open("build/dumpnow.bin", "rb").read())
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elif (address & 0x1ffff) == 0x0 and value == 0xf0:
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mu.mem_write(0x00000000, open(DCC_LOADER, "rb").read())
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mu.mem_write(0x12000000, open(DCC_LOADER, "rb").read())
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# mu.reg_write(0x)
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print("Write at", hex(address), size, hex(value))
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# if value == 0x98:
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@ -162,6 +168,22 @@ def _dcc_write_host(data):
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assert WAIT_RESPONSE, "cannot do that while running!"
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data_rd += data.to_bytes(4, "little")
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def _dcc_loader_read():
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iCount = _dcc_read_host()
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print("C:", hex(iCount))
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crc = crcmod.mkCrcFun(0x104c11db7, 0xffffffff, False, 0)
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hashData = bytearray()
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for _ in range(iCount):
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dccRead = _dcc_read_host()
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print("H:", hex(dccRead))
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hashData += dccRead.to_bytes(4, "little")
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sum = _dcc_read_host()
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hash = crc(hashData)
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assert sum == hash, f"Checksum is invalid! 0x{sum:08x} != 0x{hash:08x}"
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if __name__ == '__main__':
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import threading
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import time
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@ -169,21 +191,28 @@ if __name__ == '__main__':
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t = threading.Thread(target=test_arm, daemon=True)
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t.start()
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iCount = _dcc_read_host()
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print("C:", hex(iCount))
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for _ in range(iCount + 1):
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print("H:", hex(_dcc_read_host()))
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data_rd = b""
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_dcc_loader_read()
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print("RUN")
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_dcc_write_host(0x152 | 0x00000000)
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_dcc_write_host(0x00120000)
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_dcc_write_host(0x00000080)
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if True:
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_dcc_write_host(0x152 | 0x00000000)
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_dcc_write_host(0x00120000)
|
||||
_dcc_write_host(0x00000080)
|
||||
|
||||
WAIT_RESPONSE = False
|
||||
_dcc_loader_read()
|
||||
|
||||
WAIT_RESPONSE = False
|
||||
while len(data_rd) > 0:
|
||||
print("H:", hex(_dcc_read_host()))
|
||||
if True:
|
||||
_dcc_write_host(0x252 | 0x00000000)
|
||||
_dcc_write_host(0x00120000)
|
||||
_dcc_write_host(0x00000080)
|
||||
|
||||
WAIT_RESPONSE = False
|
||||
_dcc_loader_read()
|
||||
|
||||
time.sleep(4)
|
||||
|
||||
print("end testing")
|
||||
|
||||
# while True:
|
||||
# time.sleep(2)
|
||||
|
|
@ -66,14 +66,9 @@ DCC_RETURN CFI_Probe(DCCMemory *mem, uint32_t offset) {
|
|||
}
|
||||
|
||||
if (CFI_Type == 4) {
|
||||
#ifdef FAIL_ON_NON_CFI
|
||||
return DCC_PROBE_ERROR;
|
||||
#else
|
||||
qry.bit_width = 16;
|
||||
qry.size = 0x02000000;
|
||||
qry.block_size = 0x10000;
|
||||
CFI_Type = 3;
|
||||
#endif
|
||||
}
|
||||
|
||||
// 02 - Get Manufacturer
|
||||
|
|
@ -87,6 +82,9 @@ DCC_RETURN CFI_Probe(DCCMemory *mem, uint32_t offset) {
|
|||
|
||||
mem->manufacturer = (uint8_t)CFI_READ(offset, 0x00);
|
||||
mem->device_id = CFI_READ(offset, 0x01);
|
||||
if (CFI_Type == 4 && mem->manufacturer != 0x1c) return DCC_PROBE_ERROR;
|
||||
else if (CFI_Type == 4) CFI_Type = 3;
|
||||
|
||||
uint16_t spansion_id2 = CFI_READ(offset, 0x0e);
|
||||
uint16_t spansion_id3 = CFI_READ(offset, 0x0f);
|
||||
|
||||
|
|
@ -130,8 +128,8 @@ DCC_RETURN CFI_Probe(DCCMemory *mem, uint32_t offset) {
|
|||
mem->size = 0x00100000;
|
||||
break;
|
||||
}
|
||||
} else if (mem->manufacturer == 0x01) { // Spansion
|
||||
if ((mem->device_id & 0xff) == 0x7e && spansion_id2 == 0x2221 && mem->size == 0x01000000) mem->size = 0x800000;
|
||||
} else if (mem->manufacturer == 0x01 || mem->manufacturer == 0x04 || mem->manufacturer == 0xec || mem->manufacturer == 0xc2) { // Spansion/Fujitsu/Samsung/MXIC
|
||||
if (mem->manufacturer == 0x01 && (mem->device_id & 0xff) == 0x7e && spansion_id2 == 0x2221 && mem->size == 0x01000000) mem->size = 0x800000; // Fix S71PL129 flash misdetecting as 16MB
|
||||
PLAT_SNPRINTF(mem->name, 255, "0x%04x/0x%04x", spansion_id2, spansion_id3);
|
||||
}
|
||||
|
||||
|
|
|
|||
58
main.c
58
main.c
|
|
@ -5,6 +5,10 @@
|
|||
typedef DCC_RETURN DCC_INIT_PTR(DCCMemory *mem, uint32_t offset);
|
||||
typedef DCC_RETURN DCC_READ_PTR(DCCMemory *mem, uint32_t offset, uint32_t size, uint8_t *dest, uint32_t *dest_size);
|
||||
|
||||
#ifdef CDEFS
|
||||
const char *CFLAGS = "C:DumpNow DCC Loader. (c) 2025 Wrapper. Compile flags: " CDEFS;
|
||||
#endif
|
||||
|
||||
static uint8_t rawBuf[DCC_BUFFER_SIZE + 0x2000];
|
||||
#if HAVE_LZ4 || HAVE_MINILZO
|
||||
static uint8_t compBuf[DCC_BUFFER_SIZE + 0x4000];
|
||||
|
|
@ -22,56 +26,64 @@ size_t strlen(const char *str);
|
|||
void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
||||
DCCMemory mem[16] = { 0 };
|
||||
uint8_t mem_has_spare[16] = { 0 };
|
||||
uint32_t BUF_INIT[512];
|
||||
uint32_t BUF_INIT[2048];
|
||||
uint32_t dcc_init_offset = 0;
|
||||
uint32_t ext_mem;
|
||||
Driver *devBase;
|
||||
DCC_RETURN res;
|
||||
|
||||
/* 01 - Probe flash devices */
|
||||
for (int i = 0; i < 16; i++) {
|
||||
if (!devices[i].driver) break;
|
||||
if (!devices[i].driver) break; // Break when reaching the end of list
|
||||
|
||||
/* Probe device */
|
||||
devBase = (Driver *)absolute_to_relative(devices[i].driver);
|
||||
res = ((DCC_INIT_PTR *)absolute_to_relative(devBase->initialize))(&mem[i], devices[i].base_offset);
|
||||
if (res != DCC_OK) mem[i].type = MEMTYPE_NONE;
|
||||
|
||||
/* Print appropriate value */
|
||||
switch (mem[i].type) {
|
||||
/* Anything without spare */
|
||||
case MEMTYPE_NOR:
|
||||
case MEMTYPE_SUPERAND:
|
||||
ext_mem = DCC_MEM_EXTENDED(1, mem[i].page_size, mem[i].block_size, mem[i].size >> 20);
|
||||
mem_has_spare[i] = 0;
|
||||
/* Extended memory logic */
|
||||
WRITE_EXTMEM:
|
||||
/* Set name flag if memory name is defined */
|
||||
if (strlen(mem[i].name)) ext_mem |= 0x80;
|
||||
|
||||
/* First device info */
|
||||
BUF_INIT[dcc_init_offset++] = DCC_MEM_OK | (ext_mem << 16);
|
||||
BUF_INIT[dcc_init_offset++] = mem[i].manufacturer | (mem[i].device_id << 16);
|
||||
|
||||
/* Print additional information */
|
||||
if (strlen(mem[i].name)) {
|
||||
int sLen = strlen(mem[i].name);
|
||||
uint8_t *bufCast = (uint8_t *)BUF_INIT;
|
||||
// int sPos = 0;
|
||||
// uint8_t *sData = (uint8_t *)(BUF_INIT + dcc_init_offset);
|
||||
// BUF_INIT[dcc_init_offset++] = sLen;
|
||||
|
||||
// for (int j = 0; j < sLen; j++) {
|
||||
// BUF_INIT[dcc_init_offset++] = mem[i].name[j];
|
||||
// }
|
||||
|
||||
/* 8-bit length then name (WORD aligned) */
|
||||
BUF_INIT[dcc_init_offset] = sLen;
|
||||
INT_MEMCPY((bufCast + (dcc_init_offset << 2) + 1), mem[i].name, sLen);
|
||||
|
||||
dcc_init_offset += ALIGN4(1 + sLen) >> 2;
|
||||
}
|
||||
|
||||
/* Second device info */
|
||||
BUF_INIT[dcc_init_offset++] = ext_mem;
|
||||
break;
|
||||
|
||||
/* Regular NAND */
|
||||
case MEMTYPE_NAND:
|
||||
if (strlen(mem[i].name)) goto NAND_EXTMEM;
|
||||
if (strlen(mem[i].name)) goto NAND_EXTMEM; // Extended device info if we have additional information
|
||||
|
||||
/* Device info */
|
||||
BUF_INIT[dcc_init_offset++] = DCC_MEM_OK | (mem[i].page_size << 16);
|
||||
BUF_INIT[dcc_init_offset++] = mem[i].manufacturer | (mem[i].device_id << 16);
|
||||
mem_has_spare[i] = 1;
|
||||
break;
|
||||
|
||||
/* Anything with spare */
|
||||
case MEMTYPE_ONENAND:
|
||||
case MEMTYPE_AND:
|
||||
case MEMTYPE_AG_AND:
|
||||
|
|
@ -80,6 +92,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
mem_has_spare[i] = 1;
|
||||
goto WRITE_EXTMEM;
|
||||
|
||||
/* When device probe fails, it goes here */
|
||||
default:
|
||||
BUF_INIT[dcc_init_offset++] = DCC_MEM_OK | (DCC_MEM_NONE << 16);
|
||||
BUF_INIT[dcc_init_offset++] = 0;
|
||||
|
|
@ -88,6 +101,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
}
|
||||
}
|
||||
|
||||
/* 02 - Print buffer size */
|
||||
BUF_INIT[dcc_init_offset++] = DCC_MEM_OK | (DCC_MEM_BUFFER(0) << 16);
|
||||
BUF_INIT[dcc_init_offset++] = DCC_BUFFER_SIZE;
|
||||
|
||||
|
|
@ -101,11 +115,13 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
uint32_t srcSize;
|
||||
uint32_t destSize;
|
||||
|
||||
/* 03 - The loop */
|
||||
while (1) {
|
||||
wdog_reset();
|
||||
uint32_t cmd = DN_Packet_DCC_Read();
|
||||
|
||||
switch (cmd & 0xff) {
|
||||
/* Settings */
|
||||
case CMD_CONFIGURE:
|
||||
for (int c = 0; c < (cmd >> 0x10); c += 4) {
|
||||
DN_Packet_DCC_Read();
|
||||
|
|
@ -113,10 +129,12 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
DN_Packet_Send_One(CMD_WRITE_ERASE_STATUS(0x38, 0x6));
|
||||
break;
|
||||
|
||||
/* Get devices information */
|
||||
case CMD_GETINFO:
|
||||
DN_Packet_Send((uint8_t *)BUF_INIT, dcc_init_offset << 2);
|
||||
break;
|
||||
|
||||
/* Get memory size */
|
||||
case CMD_GETMEMSIZE:
|
||||
flashIndex = (cmd >> 8) & 0xff;
|
||||
if (flashIndex == 0) {
|
||||
|
|
@ -128,18 +146,20 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
}
|
||||
break;
|
||||
|
||||
/* Flash read */
|
||||
case CMD_READ:
|
||||
srcOffset = DN_Packet_DCC_Read();
|
||||
srcSize = DN_Packet_DCC_Read();
|
||||
flashIndex = (cmd >> 8) & 0xff;
|
||||
uint8_t algo = (cmd >> 24) & 0xff;
|
||||
|
||||
/* Check for read size not exceeding buffer */
|
||||
if (srcSize > DCC_BUFFER_SIZE) {
|
||||
DN_Packet_Send_One(CMD_READ_RESP_FAIL(DCC_INVALID_ARGS));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (flashIndex == 0) {
|
||||
if (flashIndex == 0) { // Direct read
|
||||
Jump_Read_NOR:
|
||||
#ifndef DCC_TESTING
|
||||
switch (algo) {
|
||||
|
|
@ -181,13 +201,15 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
case MEMTYPE_SUPERAND:
|
||||
case MEMTYPE_AND:
|
||||
case MEMTYPE_AG_AND:
|
||||
/* Get driver routines */
|
||||
devBase = (Driver *)absolute_to_relative(devices[flashIndex - 1].driver);
|
||||
res = ((DCC_READ_PTR *)absolute_to_relative(devBase->read))(&mem[flashIndex - 1], srcOffset, srcSize, rawBuf, &destSize);
|
||||
if (res != DCC_OK) {
|
||||
if (res != DCC_OK) { // Check if error
|
||||
DN_Packet_Send_One(CMD_READ_RESP_FAIL(res));
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Compression */
|
||||
switch (algo) {
|
||||
case CMD_READ_COMP_NONE:
|
||||
DN_Packet_WriteDirect(rawBuf, destSize);
|
||||
|
|
@ -222,15 +244,19 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
break;
|
||||
case MEMTYPE_NOR:
|
||||
default:
|
||||
/* NOR reads directly */
|
||||
srcOffset &= (mem[flashIndex - 1].size - 1);
|
||||
srcOffset += mem[flashIndex - 1].base_offset;
|
||||
goto Jump_Read_NOR;
|
||||
}
|
||||
} else {
|
||||
/* No flash found */
|
||||
DN_Packet_Send_One(CMD_READ_RESP_FAIL(DCC_FLASH_NOENT));
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
|
||||
/* Flash erase */
|
||||
case CMD_ERASE:
|
||||
srcOffset = DN_Packet_DCC_Read();
|
||||
srcSize = DN_Packet_DCC_Read();
|
||||
|
|
@ -246,6 +272,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
}
|
||||
break;
|
||||
|
||||
/* Flash write */
|
||||
case CMD_WRITE:
|
||||
flashIndex = (cmd >> 16) & 0xff;
|
||||
|
||||
|
|
@ -264,8 +291,8 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
checksum_comp = DN_Calculate_CRC32(checksum_comp, rawBuf, mem[flashIndex - 1].block_size);
|
||||
}
|
||||
if ((progType & 1) && mem_has_spare[flashIndex - 1]) {
|
||||
DN_Packet_Read(rawBuf + mem[flashIndex - 1].block_size, mem[flashIndex - 1].block_size >> 5);
|
||||
checksum_comp = DN_Calculate_CRC32(checksum_comp, rawBuf + mem[flashIndex - 1].block_size, mem[flashIndex - 1].block_size >> 5);
|
||||
DN_Packet_Read(rawBuf + ((progType & 2) ? mem[flashIndex - 1].block_size : 0), mem[flashIndex - 1].block_size >> 5);
|
||||
checksum_comp = DN_Calculate_CRC32(checksum_comp, rawBuf + ((progType & 2) ? mem[flashIndex - 1].block_size : 0), mem[flashIndex - 1].block_size >> 5);
|
||||
}
|
||||
} else {
|
||||
uint32_t comp_len = DN_Packet_DCC_Read();
|
||||
|
|
@ -285,6 +312,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
}
|
||||
break;
|
||||
|
||||
/* Catch-all for unknown commands */
|
||||
default:
|
||||
DN_Packet_Send_One(DCC_BAD_COMMAND(cmd & 0xff));
|
||||
}
|
||||
|
|
|
|||
44
makefile
44
makefile
|
|
@ -147,8 +147,8 @@ OPT = -O2
|
|||
|
||||
INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
|
||||
LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
|
||||
DEFS = $(DDEFS) $(UDEFS)
|
||||
ADEFS = $(DADEFS) $(UADEFS)
|
||||
DEFS = $(DDEFS) $(UDEFS) -DCDEFS="\"FLAGS=$(DDEFS) $(UDEFS) CPU=$(MCU) PLATFORM=$(PLATFORM) DEVICES=$(DEVICES) CONTROLLERS=$(CONTROLLERS)\""
|
||||
ADEFS = $(DADEFS) $(UADEFS) -DADEFS="\"FLAGS=$(DADEFS) $(UADEFS) CPU=$(MCU)\""
|
||||
OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
|
||||
LIBS = $(DLIBS) $(ULIBS)
|
||||
MCFLAGS = -mcpu=$(MCU)
|
||||
|
|
@ -164,6 +164,10 @@ LDFLAGS = $(MCFLAGS) -fPIC -fPIE -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PR
|
|||
# makefile rules
|
||||
#
|
||||
|
||||
ifeq ($(PLATFORM), default)
|
||||
$(warning Building without platform specific routines, specify PLATFORM= to change that)
|
||||
endif
|
||||
|
||||
all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst
|
||||
|
||||
%.o : %.c
|
||||
|
|
@ -198,19 +202,29 @@ clean:
|
|||
-rm -fR .dep
|
||||
|
||||
help:
|
||||
@echo Dumpnow DCC Loader
|
||||
@echo LZO=1 = Enable LZO Compression
|
||||
@echo LZ4=1 = Enable LZ4 Compression
|
||||
@echo LWMEM=1 = Enable LWMEM memory management
|
||||
@echo PLATFORM=(name) Select chipset platform
|
||||
@echo MCU=(MCU) = Select CPU architecture
|
||||
@echo CFI=1 = Enable CFI interface
|
||||
@echo NAND_CONTROLLER=(name) = Enable NAND controller
|
||||
@echo ONENAND_CONTROLLER=(name) = Enable OneNAND controller
|
||||
@echo SUPERAND_CONTROLLER=(name) = Enable SuperAND controller
|
||||
@echo USE_ICACHE=1 = Use instruction cache (ARM9 and later)
|
||||
@echo BP_LOADER=1 = If the chipset have broken DCC Support, compiling as Breakpoint-based loader might help
|
||||
@echo BUFFER_SIZE=(Buffer Size) = DCC Buffer Size (Default: 0x40000)
|
||||
ifeq ($(OS),Windows_NT)
|
||||
@echo > NUL
|
||||
else
|
||||
@echo > /dev/null
|
||||
endif
|
||||
$(info Dumpnow DCC Loader)
|
||||
$(info Optional libraries:)
|
||||
$(info LZO=1 = Enable LZO Compression)
|
||||
$(info LZ4=1 = Enable LZ4 Compression)
|
||||
$(info LWMEM=1 = Enable LWMEM memory management)
|
||||
$(info Target configuration:)
|
||||
$(info PLATFORM=(name) Select chipset platform)
|
||||
$(info MCU=(MCU) = Select CPU architecture)
|
||||
$(info USE_ICACHE=1 = Use instruction cache (ARM9 and later))
|
||||
$(info BP_LOADER=1 = If the chipset have broken DCC Support, compiling as Breakpoint-based loader might help)
|
||||
$(info BUFFER_SIZE=(Buffer Size) = DCC Buffer Size (Default: 0x40000))
|
||||
$(info PROJECT=(name) = Output name)
|
||||
$(info LDSCRIPT=(ld) = Linker script)
|
||||
$(info Flash devices:)
|
||||
$(info CFI=1 = Enable CFI interface)
|
||||
$(info NAND_CONTROLLER=(name) = Enable NAND controller)
|
||||
$(info ONENAND_CONTROLLER=(name) = Enable OneNAND controller)
|
||||
$(info SUPERAND_CONTROLLER=(name) = Enable SuperAND controller)
|
||||
|
||||
#
|
||||
# Include the dependency files, should be the last of the makefile
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
*/
|
||||
|
||||
#define __LZO_IN_MINILZO 1
|
||||
#define LZO_CFG_FREESTANDING 1
|
||||
|
||||
#if defined(LZO_CFG_FREESTANDING)
|
||||
# undef MINILZO_HAVE_CONFIG_H
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue