relocatable
This commit is contained in:
wrapper
parent
f63857583b
commit
7460b37bff
19 changed files with 782 additions and 463 deletions
40
build/ram.ld
40
build/ram.ld
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@ -21,6 +21,11 @@ ABT_STACK_SIZE = 0x0100;
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UND_STACK_SIZE = 0x0100;
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SVC_STACK_SIZE = 0x0100;
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PHDRS
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{
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code PT_LOAD;
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data PT_LOAD;
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}
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MEMORY
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{
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@ -49,7 +54,7 @@ SECTIONS
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*(.glue_7);
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. = ALIGN(4);
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etext = .;
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} > ram
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} > ram :code
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.data :
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{
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@ -57,12 +62,41 @@ SECTIONS
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*(.data)
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. = ALIGN(4);
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edata = .;
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_edata = .;
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PROVIDE (__data_end = .);
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} > ram
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} > ram :data
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.plt : ALIGN(4)
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{
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*(.plt)
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. = ALIGN(4);
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} > ram :code
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.got : ALIGN(4)
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{
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_sgot = .;
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_sgot_main = .;
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*(.got)
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_egot_main = .;
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} > ram :data
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.got.plt : ALIGN(4)
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{
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_sgot_plt = .;
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*(.got.plt)
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_egot_plt = .;
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_egot = .;
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_edata = .;
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} > ram :data
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.rel.dyn : ALIGN(4)
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{
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_reloc_start = .;
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*(.rel.dyn)
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} > ram :data
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.bss :
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{
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_reloc_end = .;
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PROVIDE (__bss_start = .);
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*(.bss)
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*(COMMON)
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27
crt.s
27
crt.s
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@ -47,7 +47,7 @@ _vectors:
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.global ResetHandler
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.global ExitFunction
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.global absolute_to_relative
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.extern pic_relocate
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.global DN_Packet_DCC_WaitForBP
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#if USE_BREAKPOINTS
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.global DN_Packet_DCC_ResetBPP
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@ -180,6 +180,24 @@ heap_clear_loop:
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mrc p14, 0, r0, cr1, cr0, 0
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#endif
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/* Setup PIC */
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mov r0, #0
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adr r0, _vectors
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ldr r1, =_reloc_start
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add r1, r0
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ldr r2, =_reloc_end
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add r2, r0
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ldr r3, =edata
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bl pic_relocate
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/* Setup GOT */
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ldr r9, =_sgot
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add r9, r0
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/* Jump to Main */
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mov r0, #0
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adr r0, StartAddress
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@ -222,13 +240,6 @@ IRQHandler:
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FIQHandler:
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b FIQHandler
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/* PIC routines */
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absolute_to_relative:
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mov r1, #0
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adr r1, _vectors
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add r0, r1
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bx lr
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/* Breakpoint loader routines */
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#if USE_BREAKPOINTS
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DN_Packet_DCC_WaitForBP:
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@ -16,12 +16,12 @@ static void _set_bit32(uint32_t offset, uint32_t bit_position, uint32_t bit_mask
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WRITE_U32(offset, (READ_U32(offset) & ~(bit_mask << bit_position)) | ((value & bit_mask) << bit_position));
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}
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uint32_t GET_BIT32(uint32_t offset, bitmask bitmask)
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uint32_t GET_BIT32(uint32_t offset, const bitmask bitmask)
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{
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return _get_bit32(offset, bitmask.bit_pos, bitmask.bit_mask);
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}
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void SET_BIT32(uint32_t offset, bitmask bitmask, uint32_t value)
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void SET_BIT32(uint32_t offset, const bitmask bitmask, uint32_t value)
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{
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_set_bit32(offset, bitmask.bit_pos, bitmask.bit_mask, value);
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}
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@ -38,12 +38,12 @@ static void _set_bit16(uint32_t offset, uint32_t bit_position, uint32_t bit_mask
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}
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uint16_t GET_BIT16(uint32_t offset, bitmask bitmask)
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uint16_t GET_BIT16(uint32_t offset, const bitmask bitmask)
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{
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return _get_bit16(offset, bitmask.bit_pos, bitmask.bit_mask);
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}
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void SET_BIT16(uint32_t offset, bitmask bitmask, uint16_t value)
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void SET_BIT16(uint32_t offset, const bitmask bitmask, uint16_t value)
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{
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_set_bit16(offset, bitmask.bit_pos, bitmask.bit_mask, value);
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}
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@ -60,12 +60,12 @@ static void _set_bit8(uint32_t offset, uint32_t bit_position, uint32_t bit_mask,
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WRITE_U8(offset, (READ_U8(offset) & ~(bit_mask << bit_position)) | ((value & bit_mask) << bit_position));
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}
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uint8_t GET_BIT8(uint32_t offset, bitmask bitmask)
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uint8_t GET_BIT8(uint32_t offset, const bitmask bitmask)
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{
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return _get_bit8(offset, bitmask.bit_pos, bitmask.bit_mask);
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}
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void SET_BIT8(uint32_t offset, bitmask bitmask, uint8_t value)
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void SET_BIT8(uint32_t offset, const bitmask bitmask, uint8_t value)
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{
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_set_bit8(offset, bitmask.bit_pos, bitmask.bit_mask, value);
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}
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@ -9,10 +9,10 @@ typedef struct {
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uint32_t bit_mask;
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} bitmask;
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uint8_t GET_BIT8(uint32_t offset, bitmask bitmask);
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uint16_t GET_BIT16(uint32_t offset, bitmask bitmask);
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uint32_t GET_BIT32(uint32_t offset, bitmask bitmask);
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uint8_t GET_BIT8(uint32_t offset, const bitmask bitmask);
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uint16_t GET_BIT16(uint32_t offset, const bitmask bitmask);
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uint32_t GET_BIT32(uint32_t offset, const bitmask bitmask);
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void SET_BIT8(uint32_t offset, bitmask bitmask, uint8_t value);
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void SET_BIT16(uint32_t offset, bitmask bitmask, uint16_t value);
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void SET_BIT32(uint32_t offset, bitmask bitmask, uint32_t value);
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void SET_BIT8(uint32_t offset, const bitmask bitmask, uint8_t value);
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void SET_BIT16(uint32_t offset, const bitmask bitmask, uint16_t value);
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void SET_BIT32(uint32_t offset, const bitmask bitmask, uint32_t value);
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14
dcc/pic.c
Normal file
14
dcc/pic.c
Normal file
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@ -0,0 +1,14 @@
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#include <stdint.h>
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typedef struct {
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uint32_t offset;
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uint32_t type;
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} RELOC;
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void pic_relocate(uint32_t base, uint32_t reloc_cur, uint32_t reloc_end, uint32_t data_offs) {
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while (reloc_cur < reloc_end) {
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RELOC *rel = (RELOC *)(reloc_cur);
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if (rel->type == 0x17 && rel->offset >= data_offs) rel->offset += base;
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reloc_cur += sizeof(RELOC);
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}
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}
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@ -36,6 +36,7 @@ def hook_code(uc: Uc, address, size, user_data):
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print("RSP2", hex(uc.reg_read(UC_ARM_REG_R1)))
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print("RSP3", hex(uc.reg_read(UC_ARM_REG_R2)))
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print("RSP4", hex(uc.reg_read(UC_ARM_REG_R3)))
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print("RLOC", hex(uc.reg_read(UC_ARM_REG_R9)))
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print("SP", hex(uc.reg_read(UC_ARM_REG_SP)))
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print("SP_DATA", uc.mem_read(uc.reg_read(UC_ARM_REG_SP), 0x10))
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@ -35,6 +35,7 @@ def hook_code(uc: Uc, address, size, user_data):
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print("RSP2", hex(uc.reg_read(UC_ARM_REG_R1)))
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print("RSP3", hex(uc.reg_read(UC_ARM_REG_R2)))
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print("RSP4", hex(uc.reg_read(UC_ARM_REG_R3)))
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print("RLOC", hex(uc.reg_read(UC_ARM_REG_R9)))
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print("SP", hex(uc.reg_read(UC_ARM_REG_SP)))
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print("SP_DATA", uc.mem_read(uc.reg_read(UC_ARM_REG_SP), 0x10))
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259
dcc_emu_reloc.py
Normal file
259
dcc_emu_reloc.py
Normal file
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@ -0,0 +1,259 @@
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#!/usr/bin/env python
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# Sample code for ARM of Unicorn. Nguyen Anh Quynh <aquynh@gmail.com>
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# Python sample ported by Loi Anh Tuan <loianhtuan@gmail.com>
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from __future__ import print_function
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from unicorn import *
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from unicorn.arm_const import *
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from capstone import *
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from capstone.arm import *
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import crcmod
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DEBUG_INFO = True
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DEBUG = True
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# callback for tracing basic blocks
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def hook_block(uc, address, size, user_data):
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pass
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#print(">>> Tracing basic block at 0x%x, block size = 0x%x" %(address, size))
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status_reg = 0b0100 << 28 # By default, the DCC loader can write, but not read
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rd_reg = 0
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wr_reg = 0
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DCC_LOADER = "build/dumpnow.bin"
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DCC_FW = "build/dumpnow.bin"
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# callback for tracing instructions
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def hook_code(uc: Uc, address, size, user_data):
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global status_reg, wr_reg
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try:
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#if address == 0x14001da0: uc.mem_write(0x0, b"\x01\x00\x7e\x22")
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if DEBUG and DEBUG_INFO:
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print(">>> Tracing instruction at 0x%x, instruction size = 0x%x" %(address, size))
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print("CODE:",uc.mem_read(address, size))
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print("RSP1", hex(uc.reg_read(UC_ARM_REG_R0)))
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print("RSP2", hex(uc.reg_read(UC_ARM_REG_R1)))
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print("RSP3", hex(uc.reg_read(UC_ARM_REG_R2)))
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print("RSP4", hex(uc.reg_read(UC_ARM_REG_R3)))
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print("RLOC", hex(uc.reg_read(UC_ARM_REG_R9)))
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print("SP", hex(uc.reg_read(UC_ARM_REG_SP)))
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print("SP_DATA", uc.mem_read(uc.reg_read(UC_ARM_REG_SP), 0x10))
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cs = Cs(CS_ARCH_ARM, CS_MODE_THUMB if uc.reg_read(UC_ARM_REG_CPSR) & (1 << 5) else CS_MODE_ARM)
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cs.detail = True
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ins: CsInsn = [x for x in cs.disasm(uc.mem_read(address, size), address)][0]
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if ins.id == ARM_INS_MRC:
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if ins.operands[0].value.imm == 14:
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opc_1 = ins.operands[1].value.imm
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cp_dest = ins.operands[2].value.reg
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cr_n = ins.operands[3].value.imm
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cr_m = ins.operands[4].value.imm
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opc_2 = ins.operands[5].value.imm
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if cr_n == 0:
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uc.reg_write(cp_dest, status_reg)
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elif cr_n == 1:
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print("DCC HOST -> OCD", hex(rd_reg))
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uc.reg_write(cp_dest, rd_reg)
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status_reg &= ~1 # Sets the R bit to low, indicating that the host has finished processing the data.
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uc.reg_write(UC_ARM_REG_PC, address+size) # Skip this instruction as we've already processed some DCC logic
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elif ins.id == ARM_INS_MCR:
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if ins.operands[0].value.imm == 14:
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opc_1 = ins.operands[1].value.imm
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cp_dest = ins.operands[2].value.reg
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cr_n = ins.operands[3].value.imm
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cr_m = ins.operands[4].value.imm
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opc_2 = ins.operands[5].value.imm
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if cr_n == 0:
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status_reg = uc.reg_read(cp_dest)
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elif cr_n == 1:
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wr_reg = uc.reg_read(cp_dest)
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print("DCC OCD -> HOST", hex(wr_reg))
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status_reg |= 2 # Sets the W bit to high, indicating that the debugger is ready to process the data.
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uc.reg_write(UC_ARM_REG_PC, address+size) # Skip this instruction as we've already processed some DCC logic
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except KeyboardInterrupt:
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uc.emu_stop()
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raise
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# cp = 15
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# is64 = 0
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# sec = 0
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# crn = 1
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# crm = 0
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# opc1 = 0
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# opc2 = 0
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# val = ??
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# Test ARM
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def test_arm():
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print("Emulate ARM code")
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try:
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# Initialize emulator in ARM mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_ARM)
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mu.ctl_exits_enabled(True)
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mu.ctl_set_exits([0x14000178])
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mu.mem_map(0x00000000, 32 * 1024 * 1024)
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mu.mem_map(0x12000000, 32 * 1024 * 1024)
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mu.mem_map(0x03000000, 2 * 1024 * 1024)
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# map 2MB memory for this emulation
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mu.mem_map(0x14000000, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0x14000000, open(DCC_LOADER, "rb").read())
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#mu.mem_write(0x00000000, open("cfi_32mb.bin", "rb").read())
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#mu.mem_write(0x00000000, b"\x01\x00\x7e\x22") # Infineon NOR
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#mu.mem_write(0x14000020, b"\x00\x00\x00\x00") # Infineon NOR
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#mu.mem_write(0x00000020, b"Q\0R\0Y\0\x02\0\0\0")
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#mu.mem_write(0x0000004e, (23).to_bytes(2, "little"))
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#mu.mem_write(0x14000020, b"\0\0\0\x10")
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# initialize machine registers
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mu.reg_write(UC_ARM_REG_APSR, 0xFFFFFFFF) #All application flags turned on
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# tracing all basic blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, hook_block)
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# tracing one instruction at ADDRESS with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code)
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def on_read(mu, access, address, size, value, data):
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#if DEBUG and address <= 0x14000000:
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if DEBUG and DEBUG_INFO:
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print("Read at", hex(address), size, mu.mem_read(address, size))
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def on_write(mu, access, address, size, value, data):
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if DEBUG:
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if address <= 0x14000000:
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if (address & 0x1ffff) == 0xaaa and value == 0x98:
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mu.mem_write(0x00000000, open("cfi_32mb.bin", "rb").read())
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mu.mem_write(0x12000000, open("cfi_32mb.bin", "rb").read())
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elif (address & 0x1ffff) == 0xaaa and value == 0x90:
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mu.mem_write(0x00000000, b"\x01\x00\x7e\x22")
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mu.mem_write(0x12000000, b"\x01\x00\x7e\x22")
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elif (address & 0x1ffff) == 0x0 and value == 0xf0:
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mu.mem_write(0x00000000, open(DCC_FW, "rb").read())
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mu.mem_write(0x12000000, open(DCC_FW, "rb").read())
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# mu.reg_write(0x)
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if DEBUG_INFO: print("Write at", hex(address), size, hex(value))
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# if value == 0x98:
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# mu.mem_write(0x0, open("cfi.bin", "rb").read())
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# elif value == 0xf0:
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# mu.mem_write(0x0, open("RIFF_Nor_DCC_Test.bin", "rb").read())
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# else:
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# mu.mem_write(address, value.to_bytes(size, "little"))
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def on_error(mu, access, address, size, value, data):
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if DEBUG:
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print("Error at", hex(address), size, hex(value), "in", hex(mu.reg_read(UC_ARM_REG_PC)), "lr", hex(mu.reg_read(UC_ARM_REG_LR)))
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mu.hook_add(UC_HOOK_MEM_READ, on_read)
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mu.hook_add(UC_HOOK_MEM_WRITE, on_write)
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mu.hook_add(UC_HOOK_MEM_INVALID, on_error)
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# emulate machine code in infinite time
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mu.emu_start(0x14000000, 0x1440000)
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# now print out some registers
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print(">>> Emulation done. Below is the CPU context")
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r0 = mu.reg_read(UC_ARM_REG_R0)
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r1 = mu.reg_read(UC_ARM_REG_R1)
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print(">>> R0 = 0x%x" %r0)
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print(">>> R1 = 0x%x" %r1)
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except UcError as e:
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print("ERROR: %s" % e)
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def _dcc_read_host():
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global status_reg
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if (status_reg & 2) == 0: return 0
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print("DBG READ")
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temp = wr_reg
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status_reg &= ~2 # Debugger finally processed the data and set the W bit to low.
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return temp
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def _dcc_write_host(data):
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import time
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global status_reg, rd_reg
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while _dcc_read_status_host() & 1: time.sleep(0.1)
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print("DBG WRTIE")
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rd_reg = data
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status_reg |= 1 # With the R bit set to high, the host was as motivated to process the data.
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def _dcc_read_status_host():
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return status_reg
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def _dcc_loader_read():
|
||||
while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
|
||||
iCount = _dcc_read_host()
|
||||
print("C:", hex(iCount))
|
||||
crc = crcmod.mkCrcFun(0x104c11db7, 0xffffffff, False, 0)
|
||||
hashData = bytearray()
|
||||
|
||||
for _ in range(iCount):
|
||||
while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
|
||||
dccRead = _dcc_read_host()
|
||||
print("H:", hex(dccRead))
|
||||
hashData += dccRead.to_bytes(4, "little")
|
||||
|
||||
while (_dcc_read_status_host() & 2) == 0: time.sleep(0.1)
|
||||
sum = _dcc_read_host()
|
||||
|
||||
hash = crc(hashData)
|
||||
assert sum == hash, f"Checksum is invalid! 0x{sum:08x} != 0x{hash:08x}"
|
||||
|
||||
if __name__ == '__main__':
|
||||
test_arm()
|
||||
# import threading
|
||||
# import time
|
||||
|
||||
# t = threading.Thread(target=test_arm, daemon=True)
|
||||
# t.start()
|
||||
|
||||
# _dcc_loader_read()
|
||||
# print("RUN")
|
||||
|
||||
# offs = 0
|
||||
|
||||
# if True:
|
||||
# while offs < 0x01000000:
|
||||
# _dcc_write_host(0x152 | 0x00000000)
|
||||
# _dcc_write_host(offs)
|
||||
# _dcc_write_host(0x00020000)
|
||||
|
||||
# _dcc_loader_read()
|
||||
# offs += 0x20000
|
||||
# raise Exception("continue")
|
||||
|
||||
# # if True:
|
||||
# # _dcc_write_host(0x252 | 0x00000000)
|
||||
# # _dcc_write_host(0x00120000)
|
||||
# # _dcc_write_host(0x00000080)
|
||||
|
||||
# # _dcc_loader_read()
|
||||
|
||||
# time.sleep(4)
|
||||
|
||||
# print("end testing")
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
#pragma once
|
||||
#include "dcc/dn_dcc_proto.h"
|
||||
|
||||
extern Device devices[];
|
||||
extern const Device devices[];
|
||||
|
|
@ -9,7 +9,7 @@ typedef struct {
|
|||
uint32_t bits;
|
||||
} nand_info;
|
||||
|
||||
extern nand_info flash_ids[];
|
||||
extern const nand_info flash_ids[];
|
||||
|
||||
typedef enum {
|
||||
NAND_STATUS_FAIL = 0x01,
|
||||
|
|
|
|||
|
|
@ -16,48 +16,48 @@
|
|||
#define PXA3_REG_NDCB1 PXA3_NAND_BASE_REG + 0x4C
|
||||
#define PXA3_REG_NDCB2 PXA3_NAND_BASE_REG + 0x50
|
||||
|
||||
bitmask PXA3_NDCR_SPARE_EN = {31, 0x1};
|
||||
bitmask PXA3_NDCR_ECC_EN = {30, 0x1};
|
||||
bitmask PXA3_NDCR_DMA_EN = {29, 0x1};
|
||||
bitmask PXA3_NDCR_ND_RUN = {28, 0x1};
|
||||
bitmask PXA3_NDCR_DWIDTH_C = {27, 0x1};
|
||||
bitmask PXA3_NDCR_DWIDTH_M = {26, 0x1};
|
||||
bitmask PXA3_NDCR_PAGE_SZ = {24, 0x1};
|
||||
bitmask PXA3_NDCR_NCSX = {23, 0x1};
|
||||
bitmask PXA3_NDCR_CLR_PG_CNT = {20, 0x1};
|
||||
bitmask PXA3_NDCR_STOP_ON_UNCOR = {19, 0x1};
|
||||
bitmask PXA3_NDCR_RD_ID_CNT = {16, 0x7};
|
||||
bitmask PXA3_NDCR_RA_START = {15, 0x1};
|
||||
bitmask PXA3_NDCR_PG_PER_BLK = {14, 0x1};
|
||||
bitmask PXA3_NDCR_ND_ARB_EN = {12, 0x1};
|
||||
bitmask PXA3_NDCR_INTERRUPT = {0, 0xfff};
|
||||
const bitmask PXA3_NDCR_SPARE_EN = {31, 0x1};
|
||||
const bitmask PXA3_NDCR_ECC_EN = {30, 0x1};
|
||||
const bitmask PXA3_NDCR_DMA_EN = {29, 0x1};
|
||||
const bitmask PXA3_NDCR_ND_RUN = {28, 0x1};
|
||||
const bitmask PXA3_NDCR_DWIDTH_C = {27, 0x1};
|
||||
const bitmask PXA3_NDCR_DWIDTH_M = {26, 0x1};
|
||||
const bitmask PXA3_NDCR_PAGE_SZ = {24, 0x1};
|
||||
const bitmask PXA3_NDCR_NCSX = {23, 0x1};
|
||||
const bitmask PXA3_NDCR_CLR_PG_CNT = {20, 0x1};
|
||||
const bitmask PXA3_NDCR_STOP_ON_UNCOR = {19, 0x1};
|
||||
const bitmask PXA3_NDCR_RD_ID_CNT = {16, 0x7};
|
||||
const bitmask PXA3_NDCR_RA_START = {15, 0x1};
|
||||
const bitmask PXA3_NDCR_PG_PER_BLK = {14, 0x1};
|
||||
const bitmask PXA3_NDCR_ND_ARB_EN = {12, 0x1};
|
||||
const bitmask PXA3_NDCR_INTERRUPT = {0, 0xfff};
|
||||
|
||||
bitmask PXA3_NDSR_MASK = {0, 0xfff};
|
||||
bitmask PXA3_NDSR_RDY = {12, 0x1};
|
||||
bitmask PXA3_NDSR_FLASH_RDY = {11, 0x1};
|
||||
bitmask PXA3_NDSR_CS0_PAGED = {10, 0x1};
|
||||
bitmask PXA3_NDSR_CS1_PAGED = {9, 0x1};
|
||||
bitmask PXA3_NDSR_CS0_CMDD = {8, 0x1};
|
||||
bitmask PXA3_NDSR_CS1_CMDD = {7, 0x1};
|
||||
bitmask PXA3_NDSR_CS0_BBD = {6, 0x1};
|
||||
bitmask PXA3_NDSR_CS1_BBD = {5, 0x1};
|
||||
bitmask PXA3_NDSR_UNCORERR = {4, 0x1};
|
||||
bitmask PXA3_NDSR_CORERR = {3, 0x1};
|
||||
bitmask PXA3_NDSR_WRDREQ = {2, 0x1};
|
||||
bitmask PXA3_NDSR_RDDREQ = {1, 0x1};
|
||||
bitmask PXA3_NDSR_WRCMDREQ = {0, 0x1};
|
||||
const bitmask PXA3_NDSR_MASK = {0, 0xfff};
|
||||
const bitmask PXA3_NDSR_RDY = {12, 0x1};
|
||||
const bitmask PXA3_NDSR_FLASH_RDY = {11, 0x1};
|
||||
const bitmask PXA3_NDSR_CS0_PAGED = {10, 0x1};
|
||||
const bitmask PXA3_NDSR_CS1_PAGED = {9, 0x1};
|
||||
const bitmask PXA3_NDSR_CS0_CMDD = {8, 0x1};
|
||||
const bitmask PXA3_NDSR_CS1_CMDD = {7, 0x1};
|
||||
const bitmask PXA3_NDSR_CS0_BBD = {6, 0x1};
|
||||
const bitmask PXA3_NDSR_CS1_BBD = {5, 0x1};
|
||||
const bitmask PXA3_NDSR_UNCORERR = {4, 0x1};
|
||||
const bitmask PXA3_NDSR_CORERR = {3, 0x1};
|
||||
const bitmask PXA3_NDSR_WRDREQ = {2, 0x1};
|
||||
const bitmask PXA3_NDSR_RDDREQ = {1, 0x1};
|
||||
const bitmask PXA3_NDSR_WRCMDREQ = {0, 0x1};
|
||||
|
||||
bitmask PXA3_NDCB_LEN_OVRD = {28, 0x1};
|
||||
bitmask PXA3_NDCB_ST_ROW_EN = {26, 0x1};
|
||||
bitmask PXA3_NDCB_AUTO_RS = {25, 0x1};
|
||||
bitmask PXA3_NDCB_CSEL = {24, 0x1};
|
||||
bitmask PXA3_NDCB_EXT_CMD_TYPE = {29, 0x7};
|
||||
bitmask PXA3_NDCB_CMD_TYPE = {21, 0x7};
|
||||
bitmask PXA3_NDCB_NC = {20, 0x1};
|
||||
bitmask PXA3_NDCB_DBC = {19, 0x1};
|
||||
bitmask PXA3_NDCB_ADDR_CYC = {16, 0x7};
|
||||
bitmask PXA3_NDCB_CMD2 = {8, 0xff};
|
||||
bitmask PXA3_NDCB_CMD1 = {0, 0xff};
|
||||
const bitmask PXA3_NDCB_LEN_OVRD = {28, 0x1};
|
||||
const bitmask PXA3_NDCB_ST_ROW_EN = {26, 0x1};
|
||||
const bitmask PXA3_NDCB_AUTO_RS = {25, 0x1};
|
||||
const bitmask PXA3_NDCB_CSEL = {24, 0x1};
|
||||
const bitmask PXA3_NDCB_EXT_CMD_TYPE = {29, 0x7};
|
||||
const bitmask PXA3_NDCB_CMD_TYPE = {21, 0x7};
|
||||
const bitmask PXA3_NDCB_NC = {20, 0x1};
|
||||
const bitmask PXA3_NDCB_DBC = {19, 0x1};
|
||||
const bitmask PXA3_NDCB_ADDR_CYC = {16, 0x7};
|
||||
const bitmask PXA3_NDCB_CMD2 = {8, 0xff};
|
||||
const bitmask PXA3_NDCB_CMD1 = {0, 0xff};
|
||||
|
||||
typedef enum {
|
||||
PXA3_NDCB_TYPE_READ,
|
||||
|
|
|
|||
|
|
@ -17,41 +17,41 @@
|
|||
#define MSM6250_CMD_FLASH_STATUS_CHECK 6
|
||||
#define MSM6250_CMD_FLASH_RESET_NAND 7
|
||||
|
||||
bitmask MSM6250_ADDR_SPARE_AREA_BYTE_ADDRESS = {0, 0x3f};
|
||||
bitmask MSM6250_ADDR_FLASH_PAGE_ADDRESS = {9, 0x7fffff};
|
||||
const bitmask MSM6250_ADDR_SPARE_AREA_BYTE_ADDRESS = {0, 0x3f};
|
||||
const bitmask MSM6250_ADDR_FLASH_PAGE_ADDRESS = {9, 0x7fffff};
|
||||
|
||||
bitmask MSM6250_CMD_OP_CMD = {0, 0x7};
|
||||
bitmask MSM6250_CMD_SW_CMD_EN = {3, 0x1};
|
||||
bitmask MSM6250_CMD_SW_CMD_VAL = {4, 0xff};
|
||||
bitmask MSM6250_CMD_SW_CMD_ADDR_SEL = {12, 0x1};
|
||||
bitmask MSM6250_CMD_SW_CMD1_REPLACE = {13, 0x1};
|
||||
bitmask MSM6250_CMD_SW_CMD2_REPLACE = {14, 0x1};
|
||||
const bitmask MSM6250_CMD_OP_CMD = {0, 0x7};
|
||||
const bitmask MSM6250_CMD_SW_CMD_EN = {3, 0x1};
|
||||
const bitmask MSM6250_CMD_SW_CMD_VAL = {4, 0xff};
|
||||
const bitmask MSM6250_CMD_SW_CMD_ADDR_SEL = {12, 0x1};
|
||||
const bitmask MSM6250_CMD_SW_CMD1_REPLACE = {13, 0x1};
|
||||
const bitmask MSM6250_CMD_SW_CMD2_REPLACE = {14, 0x1};
|
||||
|
||||
bitmask MSM6250_STATUS_OP_STATUS = {0, 0x7};
|
||||
bitmask MSM6250_STATUS_OP_ERR = {3, 0x1};
|
||||
bitmask MSM6250_STATUS_CORRECTABLE_ERROR = {4, 0x1};
|
||||
bitmask MSM6250_STATUS_READY_BUSY_N = {5, 0x1};
|
||||
bitmask MSM6250_STATUS_ECC_SELF_ERR = {6, 0x1};
|
||||
bitmask MSM6250_STATUS_WRITE_OP_RESULT = {7, 0x1};
|
||||
bitmask MSM6250_STATUS_OP_FAILURE = {0, 0x88};
|
||||
bitmask MSM6250_STATUS_READY_BUSY_N_STATUS = {13, 0x1};
|
||||
bitmask MSM6250_STATUS_WRITE_PROTECT = {14, 0x1};
|
||||
bitmask MSM6250_STATUS_NAND_DEVID = {15, 0xff};
|
||||
bitmask MSM6250_STATUS_NAND_MFRID = {23, 0xff};
|
||||
bitmask MSM6250_STATUS_READ_ERROR = {31, 0x1};
|
||||
const bitmask MSM6250_STATUS_OP_STATUS = {0, 0x7};
|
||||
const bitmask MSM6250_STATUS_OP_ERR = {3, 0x1};
|
||||
const bitmask MSM6250_STATUS_CORRECTABLE_ERROR = {4, 0x1};
|
||||
const bitmask MSM6250_STATUS_READY_BUSY_N = {5, 0x1};
|
||||
const bitmask MSM6250_STATUS_ECC_SELF_ERR = {6, 0x1};
|
||||
const bitmask MSM6250_STATUS_WRITE_OP_RESULT = {7, 0x1};
|
||||
const bitmask MSM6250_STATUS_OP_FAILURE = {0, 0x88};
|
||||
const bitmask MSM6250_STATUS_READY_BUSY_N_STATUS = {13, 0x1};
|
||||
const bitmask MSM6250_STATUS_WRITE_PROTECT = {14, 0x1};
|
||||
const bitmask MSM6250_STATUS_NAND_DEVID = {15, 0xff};
|
||||
const bitmask MSM6250_STATUS_NAND_MFRID = {23, 0xff};
|
||||
const bitmask MSM6250_STATUS_READ_ERROR = {31, 0x1};
|
||||
|
||||
bitmask MSM6250_CONFIG_ECC_DISABLED = {0, 0x1};
|
||||
bitmask MSM6250_CONFIG_BUSFREE_SUPPORT_SELECT = {1, 0x1};
|
||||
bitmask MSM6250_CONFIG_ECC_HALT_DIS = {2, 0x1};
|
||||
bitmask MSM6250_CONFIG_CLK_HALT_DIS = {3, 0x1};
|
||||
bitmask MSM6250_CONFIG_WIDE_NAND = {5, 0x1};
|
||||
bitmask MSM6250_CONFIG_BUFFER_MEM_WRITE_WAIT = {6, 0x1};
|
||||
bitmask MSM6250_CONFIG_ECC_ERR_SELF_DETECT = {7, 0x1};
|
||||
bitmask MSM6250_CONFIG_NAND_RECOVERY_CYCLE = {8, 0x7};
|
||||
const bitmask MSM6250_CONFIG_ECC_DISABLED = {0, 0x1};
|
||||
const bitmask MSM6250_CONFIG_BUSFREE_SUPPORT_SELECT = {1, 0x1};
|
||||
const bitmask MSM6250_CONFIG_ECC_HALT_DIS = {2, 0x1};
|
||||
const bitmask MSM6250_CONFIG_CLK_HALT_DIS = {3, 0x1};
|
||||
const bitmask MSM6250_CONFIG_WIDE_NAND = {5, 0x1};
|
||||
const bitmask MSM6250_CONFIG_BUFFER_MEM_WRITE_WAIT = {6, 0x1};
|
||||
const bitmask MSM6250_CONFIG_ECC_ERR_SELF_DETECT = {7, 0x1};
|
||||
const bitmask MSM6250_CONFIG_NAND_RECOVERY_CYCLE = {8, 0x7};
|
||||
|
||||
bitmask MSM6550_CONFIG2_ID_RD_SETUP = {0, 0x1f};
|
||||
bitmask MSM6550_CONFIG2_RD_SETUP = {5, 0x1f};
|
||||
bitmask MSM6550_CONFIG2_RD_ACTIVE = {10, 0x1f};
|
||||
bitmask MSM6550_CONFIG2_WR_HOLD = {15, 0x1f};
|
||||
bitmask MSM6550_CONFIG2_WR_ACTIVE = {20, 0x1f};
|
||||
bitmask MSM6550_CONFIG2_WR_SETUP = {25, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_ID_RD_SETUP = {0, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_RD_SETUP = {5, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_RD_ACTIVE = {10, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_WR_HOLD = {15, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_WR_ACTIVE = {20, 0x1f};
|
||||
const bitmask MSM6550_CONFIG2_WR_SETUP = {25, 0x1f};
|
||||
|
|
@ -22,52 +22,52 @@
|
|||
#define MSM6800_CMD_FLASH_STATUS_CHECK 6
|
||||
#define MSM6800_CMD_FLASH_RESET_NAND 7
|
||||
|
||||
bitmask MSM6800_ADDR_SPARE_AREA_BYTE_ADDRESS = {0, 0x3f};
|
||||
bitmask MSM6800_ADDR_FLASH_PAGE_ADDRESS = {9, 0x7fffff};
|
||||
const bitmask MSM6800_ADDR_SPARE_AREA_BYTE_ADDRESS = {0, 0x3f};
|
||||
const bitmask MSM6800_ADDR_FLASH_PAGE_ADDRESS = {9, 0x7fffff};
|
||||
|
||||
bitmask MSM6800_CMD_OP_CMD = {0, 0x7};
|
||||
bitmask MSM6800_CMD_SW_CMD_EN = {3, 0x1};
|
||||
bitmask MSM6800_CMD_SW_CMD_VAL = {4, 0xff};
|
||||
bitmask MSM6800_CMD_SW_CMD_ADDR_SEL = {12, 0x1};
|
||||
bitmask MSM6800_CMD_SW_CMD1_REPLACE = {13, 0x1};
|
||||
bitmask MSM6800_CMD_SW_CMD2_REPLACE = {14, 0x1};
|
||||
const bitmask MSM6800_CMD_OP_CMD = {0, 0x7};
|
||||
const bitmask MSM6800_CMD_SW_CMD_EN = {3, 0x1};
|
||||
const bitmask MSM6800_CMD_SW_CMD_VAL = {4, 0xff};
|
||||
const bitmask MSM6800_CMD_SW_CMD_ADDR_SEL = {12, 0x1};
|
||||
const bitmask MSM6800_CMD_SW_CMD1_REPLACE = {13, 0x1};
|
||||
const bitmask MSM6800_CMD_SW_CMD2_REPLACE = {14, 0x1};
|
||||
|
||||
bitmask MSM6800_STATUS_OP_STATUS = {0, 0x7};
|
||||
bitmask MSM6800_STATUS_OP_ERR = {3, 0x1};
|
||||
bitmask MSM6800_STATUS_CORRECTABLE_ERROR = {4, 0x1};
|
||||
bitmask MSM6800_STATUS_READY_BUSY_N = {5, 0x1};
|
||||
bitmask MSM6800_STATUS_ECC_SELF_ERR = {6, 0x1};
|
||||
bitmask MSM6800_STATUS_WRITE_OP_RESULT = {7, 0x1};
|
||||
bitmask MSM6800_STATUS_OP_FAILURE = {0, 0x88};
|
||||
bitmask MSM6800_STATUS_READY_BUSY_N_STATUS = {13, 0x1};
|
||||
bitmask MSM6800_STATUS_WRITE_PROTECT = {14, 0x1};
|
||||
bitmask MSM6800_STATUS_NAND_AUTOPROBE_DONE = {15, 0x1};
|
||||
bitmask MSM6800_STATUS_NAND_AUTOPROBE_ISLARGE = {16, 0x1};
|
||||
bitmask MSM6800_STATUS_NAND_AUTOPROBE_IS16BIT = {17, 0x1};
|
||||
bitmask MSM6800_STATUS_READ_ERROR = {31, 0x1};
|
||||
const bitmask MSM6800_STATUS_OP_STATUS = {0, 0x7};
|
||||
const bitmask MSM6800_STATUS_OP_ERR = {3, 0x1};
|
||||
const bitmask MSM6800_STATUS_CORRECTABLE_ERROR = {4, 0x1};
|
||||
const bitmask MSM6800_STATUS_READY_BUSY_N = {5, 0x1};
|
||||
const bitmask MSM6800_STATUS_ECC_SELF_ERR = {6, 0x1};
|
||||
const bitmask MSM6800_STATUS_WRITE_OP_RESULT = {7, 0x1};
|
||||
const bitmask MSM6800_STATUS_OP_FAILURE = {0, 0x88};
|
||||
const bitmask MSM6800_STATUS_READY_BUSY_N_STATUS = {13, 0x1};
|
||||
const bitmask MSM6800_STATUS_WRITE_PROTECT = {14, 0x1};
|
||||
const bitmask MSM6800_STATUS_NAND_AUTOPROBE_DONE = {15, 0x1};
|
||||
const bitmask MSM6800_STATUS_NAND_AUTOPROBE_ISLARGE = {16, 0x1};
|
||||
const bitmask MSM6800_STATUS_NAND_AUTOPROBE_IS16BIT = {17, 0x1};
|
||||
const bitmask MSM6800_STATUS_READ_ERROR = {31, 0x1};
|
||||
|
||||
bitmask MSM6800_COMMONCFG_BUFFER_MEM_WRITE_WAIT = {0, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_ECC_ERR_SELF_DETECT = {1, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_ECC_HALT_DIS = {2, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_CLK_HALT_DIS = {3, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_NAND_SEL = {4, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_DM_EN = {5, 0x1};
|
||||
bitmask MSM6800_COMMONCFG_NAND_AUTOPROBE = {6, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_BUFFER_MEM_WRITE_WAIT = {0, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_ECC_ERR_SELF_DETECT = {1, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_ECC_HALT_DIS = {2, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_CLK_HALT_DIS = {3, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_NAND_SEL = {4, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_DM_EN = {5, 0x1};
|
||||
const bitmask MSM6800_COMMONCFG_NAND_AUTOPROBE = {6, 0x1};
|
||||
|
||||
bitmask MSM6800_FLASH_NAND_DEVID = {0, 0xff};
|
||||
bitmask MSM6800_FLASH_NAND_MFRID = {8, 0xff};
|
||||
bitmask MSM6800_FLASH_NAND_EXTID = {16, 0xff};
|
||||
const bitmask MSM6800_FLASH_NAND_DEVID = {0, 0xff};
|
||||
const bitmask MSM6800_FLASH_NAND_MFRID = {8, 0xff};
|
||||
const bitmask MSM6800_FLASH_NAND_EXTID = {16, 0xff};
|
||||
|
||||
bitmask MSM6800_CONFIG1_ECC_DISABLED = {0, 0x1};
|
||||
bitmask MSM6800_CONFIG1_BUSFREE_SUPPORT_SELECT = {1, 0x1};
|
||||
bitmask MSM6800_CONFIG1_NAND_SIZE = {2, 0xf};
|
||||
bitmask MSM6800_CONFIG1_PAGE_IS_2KB = {6, 0x1};
|
||||
bitmask MSM6800_CONFIG1_WIDE_NAND = {7, 0x1};
|
||||
bitmask MSM6800_CONFIG1_NAND_RECOVERY_CYCLE = {8, 0x7};
|
||||
const bitmask MSM6800_CONFIG1_ECC_DISABLED = {0, 0x1};
|
||||
const bitmask MSM6800_CONFIG1_BUSFREE_SUPPORT_SELECT = {1, 0x1};
|
||||
const bitmask MSM6800_CONFIG1_NAND_SIZE = {2, 0xf};
|
||||
const bitmask MSM6800_CONFIG1_PAGE_IS_2KB = {6, 0x1};
|
||||
const bitmask MSM6800_CONFIG1_WIDE_NAND = {7, 0x1};
|
||||
const bitmask MSM6800_CONFIG1_NAND_RECOVERY_CYCLE = {8, 0x7};
|
||||
|
||||
bitmask MSM6800_CONFIG2_ID_RD_HOLD = {0, 0x1f};
|
||||
bitmask MSM6800_CONFIG2_RD_HOLD = {5, 0x1f};
|
||||
bitmask MSM6800_CONFIG2_RD_SETUP = {10, 0x1f};
|
||||
bitmask MSM6800_CONFIG2_WR_HOLD = {15, 0x1f};
|
||||
bitmask MSM6800_CONFIG2_WR_SETUP = {20, 0x1f};
|
||||
bitmask MSM6800_CONFIG2_WR_CS_SETUP = {25, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_ID_RD_HOLD = {0, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_RD_HOLD = {5, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_RD_SETUP = {10, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_WR_HOLD = {15, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_WR_SETUP = {20, 0x1f};
|
||||
const bitmask MSM6800_CONFIG2_WR_CS_SETUP = {25, 0x1f};
|
||||
|
|
@ -68,18 +68,18 @@
|
|||
#define MSM7200_CMD_STATUS 0x0C
|
||||
#define MSM7200_CMD_RESET_NAND 0x0D
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_LAST = {26, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_SEQ = {25, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EN_READ_CACHE_NEXT_CMD = {24, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EN_PROGRAM_PAGE_CACHE_NEXT_CMD = {20, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EXTENDED_FETCH_ID = {19, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_INTR_STATUS = {18, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_HOST_CFG = {17, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT_DATA_XFR_SIZE = {7, 0x3ff};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_LAST_PAGE = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_PAGE_ACC = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_LAST = {26, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_SEQ = {25, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EN_READ_CACHE_NEXT_CMD = {24, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EN_PROGRAM_PAGE_CACHE_NEXT_CMD = {20, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EXTENDED_FETCH_ID = {19, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_INTR_STATUS = {18, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_HOST_CFG = {17, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT_DATA_XFR_SIZE = {7, 0x3ff};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_LAST_PAGE = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_PAGE_ACC = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CMD_PAGE_ACC_NON_PAGE_ACCESS_COMMAND 0
|
||||
#define MSM7200_NAND_FLASH_CMD_PAGE_ACC_PAGE_ACCESS_COMMAND 1
|
||||
|
|
@ -99,14 +99,14 @@ bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
|||
#define MSM7200_NAND_FLASH_CMD_OP_CMD_RESERVED_E 14
|
||||
#define MSM7200_NAND_FLASH_CMD_OP_CMD_RESERVED_F 15
|
||||
|
||||
bitmask MSM7200_NAND_ADDR0_DEV_ADDR0 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR1_DEV_ADDR1 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_RESET_XFR_STEP_LOAD_DONE_STATUS = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_ONE_NAND_EN = {3, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_DM_EN = {2, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR = {1, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_ADDR0_DEV_ADDR0 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR1_DEV_ADDR1 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_RESET_XFR_STEP_LOAD_DONE_STATUS = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_ONE_NAND_EN = {3, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_DM_EN = {2, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN_DYNAMICALLY_CHANGING_THE_XFR_STEP2_IS_ENABLED 1
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR_DISABLE 0
|
||||
|
|
@ -114,20 +114,20 @@ bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
|||
#define MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL_NAND_CS0_IS_SELECTED 0
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL_NAND_CS1_IS_SELECTED 1
|
||||
|
||||
bitmask MSM7200_NANDC_EXEC_CMD_EXEC_CMD = {0, 0x1};
|
||||
const bitmask MSM7200_NANDC_EXEC_CMD_EXEC_CMD = {0, 0x1};
|
||||
#define MSM7200_NANDC_EXEC_CMD_EXEC_CMD_EXECUTE_THE_COMMAND 1
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_DEV_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_CODEWORD_CNTR = {12, 0xf};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE = {11, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_FIELD_512BYTE_DEVICE = {10, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_AUTO_DETECT_DONE = {9, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_MPU_ERROR = {8, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_PROG_ERASE_OP_RESULT = {7, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_NANDC_TIMEOUT_ERR = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_READY_BSY_N = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_OP_ERR = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_DEV_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_CODEWORD_CNTR = {12, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE = {11, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_FIELD_512BYTE_DEVICE = {10, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_AUTO_DETECT_DONE = {9, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_MPU_ERROR = {8, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_PROG_ERASE_OP_RESULT = {7, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_NANDC_TIMEOUT_ERR = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_READY_BSY_N = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_OP_ERR = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
||||
|
||||
#define MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE_NOT_A_2K_BYTE_PAGE_DEVICE 0
|
||||
#define MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE_ENUM_2K_BYTE_PAGE_DEVICE 1
|
||||
|
|
@ -154,19 +154,19 @@ bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
|||
#define MSM7200_NAND_FLASH_STATUS_OPER_STATUS_CHECK_STATUS 12
|
||||
#define MSM7200_NAND_FLASH_STATUS_OPER_STATUS_RESET_FLASH_DEVICE 13
|
||||
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_BAD_BLOCK_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_XFR_STEP2_REG_UPDATE_DONE = {9, 0x1};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_UNCORRECTABLE = {8, 0x1};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_NUM_ERRORS = {0, 0x1f};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_SET_RD_MODE_AFTER_STATUS = {31, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_STATUS_BFR_READ = {30, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES = {27, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_SPARE_SIZE_BYTES = {23, 0xf};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_ECC_PARITY_SIZE_BYTES = {19, 0xf};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_UD_SIZE_BYTES = {9, 0x3ff};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_CW_PER_PAGE = {6, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES = {3, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_BAD_BLOCK_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_XFR_STEP2_REG_UPDATE_DONE = {9, 0x1};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_UNCORRECTABLE = {8, 0x1};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_NUM_ERRORS = {0, 0x1f};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_SET_RD_MODE_AFTER_STATUS = {31, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_STATUS_BFR_READ = {30, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES = {27, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_SPARE_SIZE_BYTES = {23, 0xf};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_ECC_PARITY_SIZE_BYTES = {19, 0xf};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_UD_SIZE_BYTES = {9, 0x3ff};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_CW_PER_PAGE = {6, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES = {3, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
||||
|
||||
#define MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES_NO_ADDRESS_CYCLES 0
|
||||
#define MSM7200_NAND_DEV_CFG0_CW_PER_PAGE__1_CODEWORD_PER_PAGE 0
|
||||
|
|
@ -180,18 +180,18 @@ bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
|||
#define MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES_NO_ROW_ADDRESS_CYCLES 0
|
||||
#define MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES_NO_COLUMN_ADDRESS_CYCLES 0
|
||||
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_MODE = {28, 0x3};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ENABLE_BCH_ECC = {27, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_DISABLE_ECC_RESET_AFTER_OPDONE = {25, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_DECODER_CGC_EN = {24, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_ENCODER_CGC_EN = {23, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP = {17, 0x3f};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_IN_SPARE_AREA = {16, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_BYTE_NUM = {6, 0x3ff};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_CS_ACTIVE_BSY = {5, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_NAND_RECOVERY_CYCLES = {2, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_WIDE_FLASH = {1, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_MODE = {28, 0x3};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ENABLE_BCH_ECC = {27, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_DISABLE_ECC_RESET_AFTER_OPDONE = {25, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_DECODER_CGC_EN = {24, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_ENCODER_CGC_EN = {23, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP = {17, 0x3f};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_IN_SPARE_AREA = {16, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_BYTE_NUM = {6, 0x3ff};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_CS_ACTIVE_BSY = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_NAND_RECOVERY_CYCLES = {2, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_WIDE_FLASH = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP_ENUM_2_CLOCK_CYCLE_GAP 0
|
||||
#define MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP_ENUM_4_CLOCK_CYCLES_GAP 1
|
||||
|
|
@ -210,57 +210,57 @@ bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
|||
#define MSM7200_NAND_DEV_CFG1_WIDE_FLASH_ENUM_8_BIT_DATA_BUS 0
|
||||
#define MSM7200_NAND_DEV_CFG1_WIDE_FLASH_ENUM_16_BIT_DATA_BUS 1
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_READ_ID_READ_ID = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_READ_STATUS_ECC_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_READ_STATUS_DEV_STATUS = {0, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_DATA_IN = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_ADDR_OUT = {14, 0x3};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT_EN = {13, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN = {10, 0x7};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS5_N = {9, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS4_N = {8, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS3_N = {7, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS2_N = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS1_N = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS0_N = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_ALE = {3, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CLE = {2, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_WE_N = {1, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_RE_N = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_ID_READ_ID = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_STATUS_ECC_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_STATUS_DEV_STATUS = {0, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_DATA_IN = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_ADDR_OUT = {14, 0x3};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT_EN = {13, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN = {10, 0x7};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS5_N = {9, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS4_N = {8, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS3_N = {7, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS2_N = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS1_N = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS0_N = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_ALE = {3, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CLE = {2, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_WE_N = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_RE_N = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_DONT_READ 0
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_CONFIG_DATA_15_0 1
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_CONFIG_DATA_31_16 2
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_READ_STATUS_15_0 3
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_MODE_CONFIG_ACC = {0, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_STATUS_CONFIG_MODE = {0, 0x1};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_ADDR_BUS_HOLD_CYCLE = {19, 0x1};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_DATA_START_ADDR = {0, 0xffff};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO1 = {14, 0x3f};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO0 = {0, 0x3fff};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER = {30, 0x3};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_STEP1_WAIT = {26, 0xf};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_AOUT_EN = {25, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_DATA_EN = {24, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_CE_EN = {23, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_CLE_EN = {22, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_ALE_PIN = {21, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_WE_EN = {20, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_RE_EN = {19, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_WIDE = {18, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_SEQ_STEP_NUMBER = {14, 0x3};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_STEP1_WAIT = {10, 0xf};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_AOUT_EN = {9, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_DATA_EN = {8, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_CE_EN = {7, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_CLE_EN = {6, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_ALE_PIN = {5, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_WE_EN = {4, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_RE_EN = {3, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_WIDE = {2, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_MODE_CONFIG_ACC = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_STATUS_CONFIG_MODE = {0, 0x1};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_ADDR_BUS_HOLD_CYCLE = {19, 0x1};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_DATA_START_ADDR = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO1 = {14, 0x3f};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO0 = {0, 0x3fff};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER = {30, 0x3};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_STEP1_WAIT = {26, 0xf};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_AOUT_EN = {25, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_DATA_EN = {24, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_CE_EN = {23, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_CLE_EN = {22, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_ALE_PIN = {21, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_WE_EN = {20, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_RE_EN = {19, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_WIDE = {18, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_SEQ_STEP_NUMBER = {14, 0x3};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_STEP1_WAIT = {10, 0xf};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_AOUT_EN = {9, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_DATA_EN = {8, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_CE_EN = {7, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_CLE_EN = {6, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_ALE_PIN = {5, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_WE_EN = {4, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_RE_EN = {3, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_WIDE = {2, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
||||
|
||||
#define MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER_SIMPLE_STEP 0
|
||||
#define MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER_LOOP_START 1
|
||||
|
|
@ -302,42 +302,42 @@ bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
|||
#define MSM7200_FLASH_XFR_STEP_DATA_WIDE_USE_8_BIT_DATA_BUS_FOR_DATA 0
|
||||
#define MSM7200_FLASH_XFR_STEP_DATA_WIDE_USE16_BIT_DATA_BUS_FOR_DATA 1
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD_WRITE_START = {24, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_WRITE_ADDR = {16, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_ERASE_START = {8, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_ERASE_ADDR = {0, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_WRITE_START = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_WRITE_ADDR = {16, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_ERASE_START = {8, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_ERASE_ADDR = {0, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_PARAMETER_PAGE_CODE = {24, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_SEQ_READ_START_VLD = {4, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_ERASE_START_VLD = {3, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_WRITE_START_VLD = {2, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_STOP_VLD = {1, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_START_VLD = {0, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_PARAMETER_PAGE_CODE = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_SEQ_READ_START_VLD = {4, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_ERASE_START_VLD = {3, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_WRITE_START_VLD = {2, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_STOP_VLD = {1, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_START_VLD = {0, 0x1};
|
||||
|
||||
bitmask MSM7200_EBI2_MISR_SIG_REG_EBI2_MISR_SIG = {0, 0xffffffff};
|
||||
const bitmask MSM7200_EBI2_MISR_SIG_REG_EBI2_MISR_SIG = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_NAND_ADDR2_DEV_ADDR2 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR3_DEV_ADDR3 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR4_DEV_ADDR4 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR5_DEV_ADDR5 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR2_DEV_ADDR2 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR3_DEV_ADDR3 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR4_DEV_ADDR4 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR5_DEV_ADDR5 = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_LAST = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_LAST = {24, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_SEQ = {16, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_SEQ = {16, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_WRITE_START_CACHE = {0, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_WRITE_START_CACHE = {0, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD4 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD3 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD4 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD3 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD6 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD5 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD6 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD5 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD8 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD7 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD8 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD7 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_NAND_ADDR6_DEV_ADDR6 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR6_DEV_ADDR6 = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_EBI2_ECC_BUF_CFG_NUM_STEPS = {0, 0x3ff};
|
||||
const bitmask MSM7200_EBI2_ECC_BUF_CFG_NUM_STEPS = {0, 0x3ff};
|
||||
|
||||
bitmask MSM7200_FLASH_BUFF0_ACC_BUFF_DATA = {0, 0xffffffff};
|
||||
const bitmask MSM7200_FLASH_BUFF0_ACC_BUFF_DATA = {0, 0xffffffff};
|
||||
|
|
@ -43,61 +43,61 @@
|
|||
#define S3C2412_NFSECC 0x3C
|
||||
|
||||
/* S3C2410 bits */
|
||||
bitmask S3C2410_NFCONF_EN = {15, 0x1};
|
||||
bitmask S3C2410_NFCONF_INITECC = {12, 0x1};
|
||||
bitmask S3C2410_NFCONF_NFCE = {11, 0x1};
|
||||
bitmask S3C2410_NFCONF_TACLS = {8, 0x7};
|
||||
bitmask S3C2410_NFCONF_TWRPH0 = {4, 0x7};
|
||||
bitmask S3C2410_NFCONF_TWRPH1 = {0, 0x7};
|
||||
const bitmask S3C2410_NFCONF_EN = {15, 0x1};
|
||||
const bitmask S3C2410_NFCONF_INITECC = {12, 0x1};
|
||||
const bitmask S3C2410_NFCONF_NFCE = {11, 0x1};
|
||||
const bitmask S3C2410_NFCONF_TACLS = {8, 0x7};
|
||||
const bitmask S3C2410_NFCONF_TWRPH0 = {4, 0x7};
|
||||
const bitmask S3C2410_NFCONF_TWRPH1 = {0, 0x7};
|
||||
|
||||
bitmask S3C2410_NFSTAT_BUSY = {0, 0x1};
|
||||
const bitmask S3C2410_NFSTAT_BUSY = {0, 0x1};
|
||||
|
||||
/* S3C2440 bits */
|
||||
bitmask S3C2440_2412_NFCONF_BUSWIDTH = {0, 0x1};
|
||||
const bitmask S3C2440_2412_NFCONF_BUSWIDTH = {0, 0x1};
|
||||
#define S3C2440_NFCONF_BUSWIDTH_8 0
|
||||
#define S3C2440_NFCONF_BUSWIDTH_16 1
|
||||
|
||||
bitmask S3C2440_2412_NFCONF_TACLS = {12, 0x3};
|
||||
bitmask S3C2440_2412_NFCONF_TWRPH0 = {8, 0x7};
|
||||
bitmask S3C2440_2412_NFCONF_TWRPH1 = {4, 0x7};
|
||||
const bitmask S3C2440_2412_NFCONF_TACLS = {12, 0x3};
|
||||
const bitmask S3C2440_2412_NFCONF_TWRPH0 = {8, 0x7};
|
||||
const bitmask S3C2440_2412_NFCONF_TWRPH1 = {4, 0x7};
|
||||
|
||||
bitmask S3C2440_NFCONT_LOCKTIGHT = {13, 0x1};
|
||||
bitmask S3C2440_NFCONT_SOFTLOCK = {12, 0x1};
|
||||
bitmask S3C2440_NFCONT_ILLEGALACC_EN = {10, 0x1};
|
||||
bitmask S3C2440_NFCONT_RNBINT_EN = {9, 0x1};
|
||||
bitmask S3C2440_NFCONT_RN_FALLING = {8, 0x1};
|
||||
bitmask S3C2440_NFCONT_SPARE_ECCLOCK = {6, 0x1};
|
||||
bitmask S3C2440_NFCONT_MAIN_ECCLOCK = {5, 0x1};
|
||||
bitmask S3C2440_NFCONT_INITECC = {4, 0x1};
|
||||
bitmask S3C2440_NFCONT_NFCE = {1, 0x1};
|
||||
bitmask S3C2440_2412_NFCONT_ENABLE = {0, 0x1};
|
||||
const bitmask S3C2440_NFCONT_LOCKTIGHT = {13, 0x1};
|
||||
const bitmask S3C2440_NFCONT_SOFTLOCK = {12, 0x1};
|
||||
const bitmask S3C2440_NFCONT_ILLEGALACC_EN = {10, 0x1};
|
||||
const bitmask S3C2440_NFCONT_RNBINT_EN = {9, 0x1};
|
||||
const bitmask S3C2440_NFCONT_RN_FALLING = {8, 0x1};
|
||||
const bitmask S3C2440_NFCONT_SPARE_ECCLOCK = {6, 0x1};
|
||||
const bitmask S3C2440_NFCONT_MAIN_ECCLOCK = {5, 0x1};
|
||||
const bitmask S3C2440_NFCONT_INITECC = {4, 0x1};
|
||||
const bitmask S3C2440_NFCONT_NFCE = {1, 0x1};
|
||||
const bitmask S3C2440_2412_NFCONT_ENABLE = {0, 0x1};
|
||||
|
||||
bitmask S3C2440_NFSTAT_READY = {0, 0x1};
|
||||
bitmask S3C2440_NFSTAT_NCE = {1, 0x1};
|
||||
bitmask S3C2440_NFSTAT_RNB_CHANGE = {2, 0x1};
|
||||
bitmask S3C2440_NFSTAT_ILLEGAL_ACCESS = {3, 0x1};
|
||||
const bitmask S3C2440_NFSTAT_READY = {0, 0x1};
|
||||
const bitmask S3C2440_NFSTAT_NCE = {1, 0x1};
|
||||
const bitmask S3C2440_NFSTAT_RNB_CHANGE = {2, 0x1};
|
||||
const bitmask S3C2440_NFSTAT_ILLEGAL_ACCESS = {3, 0x1};
|
||||
|
||||
/* S3C2412 bits */
|
||||
bitmask S3C2412_NFCONF_NANDBOOT = {31, 0x1};
|
||||
bitmask S3C2412_NFCONF_ECCCLKCON = {30, 0x1};
|
||||
bitmask S3C2412_NFCONF_ECC_MLC = {24, 0x1};
|
||||
bitmask S3C2412_NFCONT_ECC4_DIRWR = {18, 0x1};
|
||||
bitmask S3C2412_NFCONT_LOCKTIGHT = {17, 0x1};
|
||||
bitmask S3C2412_NFCONT_SOFTLOCK = {16, 0x1};
|
||||
bitmask S3C2412_NFCONT_ECC4_ENCINT = {13, 0x1};
|
||||
bitmask S3C2412_NFCONT_ECC4_DECINT = {12, 0x1};
|
||||
bitmask S3C2412_NFCONT_MAIN_ECC_LOCK = {7, 0x1};
|
||||
bitmask S3C2412_NFCONT_MAIN_SECONDARY_ECC_LOCK = {6, 0x1};
|
||||
bitmask S3C2412_NFCONT_INIT_MAIN_ECC = {5, 0x1};
|
||||
bitmask S3C2412_NFCONT_INIT_SECONDARY_ECC = {4, 0x1};
|
||||
bitmask S3C2412_NFCONT_nFCE1 = {2, 0x1};
|
||||
bitmask S3C2412_NFCONT_nFCE0 = {1, 0x1};
|
||||
const bitmask S3C2412_NFCONF_NANDBOOT = {31, 0x1};
|
||||
const bitmask S3C2412_NFCONF_ECCCLKCON = {30, 0x1};
|
||||
const bitmask S3C2412_NFCONF_ECC_MLC = {24, 0x1};
|
||||
const bitmask S3C2412_NFCONT_ECC4_DIRWR = {18, 0x1};
|
||||
const bitmask S3C2412_NFCONT_LOCKTIGHT = {17, 0x1};
|
||||
const bitmask S3C2412_NFCONT_SOFTLOCK = {16, 0x1};
|
||||
const bitmask S3C2412_NFCONT_ECC4_ENCINT = {13, 0x1};
|
||||
const bitmask S3C2412_NFCONT_ECC4_DECINT = {12, 0x1};
|
||||
const bitmask S3C2412_NFCONT_MAIN_ECC_LOCK = {7, 0x1};
|
||||
const bitmask S3C2412_NFCONT_MAIN_SECONDARY_ECC_LOCK = {6, 0x1};
|
||||
const bitmask S3C2412_NFCONT_INIT_MAIN_ECC = {5, 0x1};
|
||||
const bitmask S3C2412_NFCONT_INIT_SECONDARY_ECC = {4, 0x1};
|
||||
const bitmask S3C2412_NFCONT_nFCE1 = {2, 0x1};
|
||||
const bitmask S3C2412_NFCONT_nFCE0 = {1, 0x1};
|
||||
|
||||
bitmask S3C2412_NFSTAT_ECC_ENCDONE = {7, 0x1};
|
||||
bitmask S3C2412_NFSTAT_ECC_DECDONE = {6, 0x1};
|
||||
bitmask S3C2412_NFSTAT_ILLEGAL_ACCESS = {5, 0x1};
|
||||
bitmask S3C2412_NFSTAT_RnB_CHANGE = {4, 0x1};
|
||||
bitmask S3C2412_NFSTAT_nFCE1 = {3, 0x1};
|
||||
bitmask S3C2412_NFSTAT_nFCE0 = {2, 0x1};
|
||||
bitmask S3C2412_NFSTAT_Res1 = {1, 0x1};
|
||||
bitmask S3C2412_NFSTAT_READY = {0, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_ECC_ENCDONE = {7, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_ECC_DECDONE = {6, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_ILLEGAL_ACCESS = {5, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_RnB_CHANGE = {4, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_nFCE1 = {3, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_nFCE0 = {2, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_Res1 = {1, 0x1};
|
||||
const bitmask S3C2412_NFSTAT_READY = {0, 0x1};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#include "controller/controller.h"
|
||||
#include "dcc/dn_dcc_proto.h"
|
||||
|
||||
nand_info flash_ids[] = {
|
||||
const nand_info flash_ids[] = {
|
||||
{0x6e, 0x100, 0x100000, 0x1000, 8},
|
||||
{0x64, 0x100, 0x200000, 0x1000, 8},
|
||||
{0xe8, 0x100, 0x100000, 0x1000, 8},
|
||||
|
|
|
|||
|
|
@ -68,18 +68,18 @@
|
|||
#define MSM7200_CMD_STATUS 0x0C
|
||||
#define MSM7200_CMD_RESET_NAND 0x0D
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_LAST = {26, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_SEQ = {25, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EN_READ_CACHE_NEXT_CMD = {24, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EN_PROGRAM_PAGE_CACHE_NEXT_CMD = {20, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_EXTENDED_FETCH_ID = {19, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_INTR_STATUS = {18, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_HOST_CFG = {17, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT_DATA_XFR_SIZE = {7, 0x3ff};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_LAST_PAGE = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_PAGE_ACC = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_LAST = {26, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_READ_CACHE_SEQ = {25, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EN_READ_CACHE_NEXT_CMD = {24, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EN_PROGRAM_PAGE_CACHE_NEXT_CMD = {20, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_EXTENDED_FETCH_ID = {19, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_INTR_STATUS = {18, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_ONE_NAND_HOST_CFG = {17, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT_DATA_XFR_SIZE = {7, 0x3ff};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_AUTO_DETECT = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_LAST_PAGE = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_PAGE_ACC = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CMD_PAGE_ACC_NON_PAGE_ACCESS_COMMAND 0
|
||||
#define MSM7200_NAND_FLASH_CMD_PAGE_ACC_PAGE_ACCESS_COMMAND 1
|
||||
|
|
@ -99,14 +99,14 @@ bitmask MSM7200_NAND_FLASH_CMD_OP_CMD = {0, 0xf};
|
|||
#define MSM7200_NAND_FLASH_CMD_OP_CMD_RESERVED_E 14
|
||||
#define MSM7200_NAND_FLASH_CMD_OP_CMD_RESERVED_F 15
|
||||
|
||||
bitmask MSM7200_NAND_ADDR0_DEV_ADDR0 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR1_DEV_ADDR1 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_RESET_XFR_STEP_LOAD_DONE_STATUS = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_ONE_NAND_EN = {3, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_DM_EN = {2, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR = {1, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_ADDR0_DEV_ADDR0 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR1_DEV_ADDR1 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_RESET_XFR_STEP_LOAD_DONE_STATUS = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_ONE_NAND_EN = {3, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_DM_EN = {2, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_XFR_STEP2_SAFE_REG_EN_DYNAMICALLY_CHANGING_THE_XFR_STEP2_IS_ENABLED 1
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_PARTIAL_XFR_DISABLE 0
|
||||
|
|
@ -114,20 +114,20 @@ bitmask MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL = {0, 0x1};
|
|||
#define MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL_NAND_CS0_IS_SELECTED 0
|
||||
#define MSM7200_NAND_FLASH_CHIP_SELECT_NAND_DEV_SEL_NAND_CS1_IS_SELECTED 1
|
||||
|
||||
bitmask MSM7200_NANDC_EXEC_CMD_EXEC_CMD = {0, 0x1};
|
||||
const bitmask MSM7200_NANDC_EXEC_CMD_EXEC_CMD = {0, 0x1};
|
||||
#define MSM7200_NANDC_EXEC_CMD_EXEC_CMD_EXECUTE_THE_COMMAND 1
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_DEV_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_CODEWORD_CNTR = {12, 0xf};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE = {11, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_FIELD_512BYTE_DEVICE = {10, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_AUTO_DETECT_DONE = {9, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_MPU_ERROR = {8, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_PROG_ERASE_OP_RESULT = {7, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_NANDC_TIMEOUT_ERR = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_READY_BSY_N = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_OP_ERR = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_DEV_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_CODEWORD_CNTR = {12, 0xf};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE = {11, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_FIELD_512BYTE_DEVICE = {10, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_AUTO_DETECT_DONE = {9, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_MPU_ERROR = {8, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_PROG_ERASE_OP_RESULT = {7, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_NANDC_TIMEOUT_ERR = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_READY_BSY_N = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_OP_ERR = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
||||
|
||||
#define MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE_NOT_A_2K_BYTE_PAGE_DEVICE 0
|
||||
#define MSM7200_NAND_FLASH_STATUS_FIELD_2KBYTE_DEVICE_ENUM_2K_BYTE_PAGE_DEVICE 1
|
||||
|
|
@ -154,19 +154,19 @@ bitmask MSM7200_NAND_FLASH_STATUS_OPER_STATUS = {0, 0xf};
|
|||
#define MSM7200_NAND_FLASH_STATUS_OPER_STATUS_CHECK_STATUS 12
|
||||
#define MSM7200_NAND_FLASH_STATUS_OPER_STATUS_RESET_FLASH_DEVICE 13
|
||||
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_BAD_BLOCK_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_XFR_STEP2_REG_UPDATE_DONE = {9, 0x1};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_UNCORRECTABLE = {8, 0x1};
|
||||
bitmask MSM7200_NANDC_BUFFER_STATUS_NUM_ERRORS = {0, 0x1f};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_SET_RD_MODE_AFTER_STATUS = {31, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_STATUS_BFR_READ = {30, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES = {27, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_SPARE_SIZE_BYTES = {23, 0xf};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_ECC_PARITY_SIZE_BYTES = {19, 0xf};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_UD_SIZE_BYTES = {9, 0x3ff};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_CW_PER_PAGE = {6, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES = {3, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_BAD_BLOCK_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_XFR_STEP2_REG_UPDATE_DONE = {9, 0x1};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_UNCORRECTABLE = {8, 0x1};
|
||||
const bitmask MSM7200_NANDC_BUFFER_STATUS_NUM_ERRORS = {0, 0x1f};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_SET_RD_MODE_AFTER_STATUS = {31, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_STATUS_BFR_READ = {30, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES = {27, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_SPARE_SIZE_BYTES = {23, 0xf};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_ECC_PARITY_SIZE_BYTES = {19, 0xf};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_UD_SIZE_BYTES = {9, 0x3ff};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_CW_PER_PAGE = {6, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES = {3, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
||||
|
||||
#define MSM7200_NAND_DEV_CFG0_NUM_ADDR_CYCLES_NO_ADDRESS_CYCLES 0
|
||||
#define MSM7200_NAND_DEV_CFG0_CW_PER_PAGE__1_CODEWORD_PER_PAGE 0
|
||||
|
|
@ -180,18 +180,18 @@ bitmask MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES = {0, 0x7};
|
|||
#define MSM7200_NAND_DEV_CFG0_ROW_ADDR_CYCLES_NO_ROW_ADDRESS_CYCLES 0
|
||||
#define MSM7200_NAND_DEV_CFG0_COL_ADDR_CYCLES_NO_COLUMN_ADDRESS_CYCLES 0
|
||||
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_MODE = {28, 0x3};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ENABLE_BCH_ECC = {27, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_DISABLE_ECC_RESET_AFTER_OPDONE = {25, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_DECODER_CGC_EN = {24, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_ENCODER_CGC_EN = {23, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP = {17, 0x3f};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_IN_SPARE_AREA = {16, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_BYTE_NUM = {6, 0x3ff};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_CS_ACTIVE_BSY = {5, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_NAND_RECOVERY_CYCLES = {2, 0x7};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_WIDE_FLASH = {1, 0x1};
|
||||
bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_MODE = {28, 0x3};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ENABLE_BCH_ECC = {27, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_DISABLE_ECC_RESET_AFTER_OPDONE = {25, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_DECODER_CGC_EN = {24, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_ENCODER_CGC_EN = {23, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP = {17, 0x3f};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_IN_SPARE_AREA = {16, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_BAD_BLOCK_BYTE_NUM = {6, 0x3ff};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_CS_ACTIVE_BSY = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_NAND_RECOVERY_CYCLES = {2, 0x7};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_WIDE_FLASH = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP_ENUM_2_CLOCK_CYCLE_GAP 0
|
||||
#define MSM7200_NAND_DEV_CFG1_WR_RD_BSY_GAP_ENUM_4_CLOCK_CYCLES_GAP 1
|
||||
|
|
@ -210,57 +210,57 @@ bitmask MSM7200_NAND_DEV_CFG1_ECC_DISABLE = {0, 0x1};
|
|||
#define MSM7200_NAND_DEV_CFG1_WIDE_FLASH_ENUM_8_BIT_DATA_BUS 0
|
||||
#define MSM7200_NAND_DEV_CFG1_WIDE_FLASH_ENUM_16_BIT_DATA_BUS 1
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_READ_ID_READ_ID = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_READ_STATUS_ECC_STATUS = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_READ_STATUS_DEV_STATUS = {0, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_DATA_IN = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT = {16, 0xffff};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_ADDR_OUT = {14, 0x3};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT_EN = {13, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN = {10, 0x7};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS5_N = {9, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS4_N = {8, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS3_N = {7, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS2_N = {6, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS1_N = {5, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CS0_N = {4, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_ALE = {3, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_CLE = {2, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_WE_N = {1, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_RE_N = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_ID_READ_ID = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_STATUS_ECC_STATUS = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_READ_STATUS_DEV_STATUS = {0, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_DATA_IN = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT = {16, 0xffff};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_ADDR_OUT = {14, 0x3};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_OUT_EN = {13, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN = {10, 0x7};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS5_N = {9, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS4_N = {8, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS3_N = {7, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS2_N = {6, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS1_N = {5, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CS0_N = {4, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_ALE = {3, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_CLE = {2, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_WE_N = {1, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_RE_N = {0, 0x1};
|
||||
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_DONT_READ 0
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_CONFIG_DATA_15_0 1
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_CONFIG_DATA_31_16 2
|
||||
#define MSM7200_NAND_FLASH_CONFIG_DATA_IN_EN_WRITE_NAND_FLASH_READ_STATUS_15_0 3
|
||||
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_MODE_CONFIG_ACC = {0, 0x1};
|
||||
bitmask MSM7200_NAND_FLASH_CONFIG_STATUS_CONFIG_MODE = {0, 0x1};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_ADDR_BUS_HOLD_CYCLE = {19, 0x1};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_DATA_START_ADDR = {0, 0xffff};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO1 = {14, 0x3f};
|
||||
bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO0 = {0, 0x3fff};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER = {30, 0x3};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_STEP1_WAIT = {26, 0xf};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_AOUT_EN = {25, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_DATA_EN = {24, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_CE_EN = {23, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_CLE_EN = {22, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_ALE_PIN = {21, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_WE_EN = {20, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_RE_EN = {19, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_CMD_WIDE = {18, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_SEQ_STEP_NUMBER = {14, 0x3};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_STEP1_WAIT = {10, 0xf};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_AOUT_EN = {9, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_DATA_EN = {8, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_CE_EN = {7, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_CLE_EN = {6, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_ALE_PIN = {5, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_WE_EN = {4, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_RE_EN = {3, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_DATA_WIDE = {2, 0x1};
|
||||
bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_MODE_CONFIG_ACC = {0, 0x1};
|
||||
const bitmask MSM7200_NAND_FLASH_CONFIG_STATUS_CONFIG_MODE = {0, 0x1};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_ADDR_BUS_HOLD_CYCLE = {19, 0x1};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_QSC6270_DATA_START_ADDR = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO1 = {14, 0x3f};
|
||||
const bitmask MSM7200_FLASH_MACRO1_REG_FLASH_DATA_MACRO0 = {0, 0x3fff};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER = {30, 0x3};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_STEP1_WAIT = {26, 0xf};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_AOUT_EN = {25, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_DATA_EN = {24, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_CE_EN = {23, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_CLE_EN = {22, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_ALE_PIN = {21, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_WE_EN = {20, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_RE_EN = {19, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_CMD_WIDE = {18, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_SEQ_STEP_NUMBER = {14, 0x3};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_STEP1_WAIT = {10, 0xf};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_AOUT_EN = {9, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_DATA_EN = {8, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_CE_EN = {7, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_CLE_EN = {6, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_ALE_PIN = {5, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_WE_EN = {4, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_RE_EN = {3, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_DATA_WIDE = {2, 0x1};
|
||||
const bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
||||
|
||||
#define MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER_SIMPLE_STEP 0
|
||||
#define MSM7200_FLASH_XFR_STEP_CMD_SEQ_STEP_NUMBER_LOOP_START 1
|
||||
|
|
@ -302,45 +302,45 @@ bitmask MSM7200_FLASH_XFR_STEP_EXTA_READ_WAIT = {0, 0x3};
|
|||
#define MSM7200_FLASH_XFR_STEP_DATA_WIDE_USE_8_BIT_DATA_BUS_FOR_DATA 0
|
||||
#define MSM7200_FLASH_XFR_STEP_DATA_WIDE_USE16_BIT_DATA_BUS_FOR_DATA 1
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD_WRITE_START = {24, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_WRITE_ADDR = {16, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_ERASE_START = {8, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_ERASE_ADDR = {0, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_WRITE_START = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_WRITE_ADDR = {16, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_ERASE_START = {8, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_ERASE_ADDR = {0, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_PARAMETER_PAGE_CODE = {24, 0xff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_SEQ_READ_START_VLD = {4, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_ERASE_START_VLD = {3, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_WRITE_START_VLD = {2, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_STOP_VLD = {1, 0x1};
|
||||
bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_START_VLD = {0, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_PARAMETER_PAGE_CODE = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_SEQ_READ_START_VLD = {4, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_ERASE_START_VLD = {3, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_WRITE_START_VLD = {2, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_STOP_VLD = {1, 0x1};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD_VLD_READ_START_VLD = {0, 0x1};
|
||||
|
||||
bitmask MSM7200_EBI2_MISR_SIG_REG_EBI2_MISR_SIG = {0, 0xffffffff};
|
||||
const bitmask MSM7200_EBI2_MISR_SIG_REG_EBI2_MISR_SIG = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_NAND_ADDR2_DEV_ADDR2 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR3_DEV_ADDR3 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR4_DEV_ADDR4 = {0, 0xffffffff};
|
||||
bitmask MSM7200_NAND_ADDR5_DEV_ADDR5 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR2_DEV_ADDR2 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR3_DEV_ADDR3 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR4_DEV_ADDR4 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR5_DEV_ADDR5 = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_LAST = {24, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_LAST = {24, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_SEQ = {16, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_READ_CACHE_SEQ = {16, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD3_WRITE_START_CACHE = {0, 0xff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD3_WRITE_START_CACHE = {0, 0xff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD4 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD3 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD4 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD4_GP_CMD3 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD6 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD5 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD6 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD5_GP_CMD5 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD8 = {16, 0xffff};
|
||||
bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD7 = {0, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD8 = {16, 0xffff};
|
||||
const bitmask MSM7200_FLASH_DEV_CMD6_GP_CMD7 = {0, 0xffff};
|
||||
|
||||
bitmask MSM7200_NAND_ADDR6_DEV_ADDR6 = {0, 0xffffffff};
|
||||
const bitmask MSM7200_NAND_ADDR6_DEV_ADDR6 = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_EBI2_ECC_BUF_CFG_NUM_STEPS = {0, 0x3ff};
|
||||
const bitmask MSM7200_EBI2_ECC_BUF_CFG_NUM_STEPS = {0, 0x3ff};
|
||||
|
||||
bitmask MSM7200_FLASH_BUFF0_ACC_BUFF_DATA = {0, 0xffffffff};
|
||||
const bitmask MSM7200_FLASH_BUFF0_ACC_BUFF_DATA = {0, 0xffffffff};
|
||||
|
||||
bitmask MSM7200_SFLASHC_EXEC_CMD_BUSY = {0, 0x1};
|
||||
bitmask MSM7200_SFLASHC_OPER_STATUS = {0, 0xf};
|
||||
const bitmask MSM7200_SFLASHC_EXEC_CMD_BUSY = {0, 0x1};
|
||||
const bitmask MSM7200_SFLASHC_OPER_STATUS = {0, 0xf};
|
||||
12
main.c
12
main.c
|
|
@ -9,7 +9,7 @@ typedef DCC_RETURN DCC_ERASE_PTR(DCCMemory *mem, uint32_t offset, uint32_t size)
|
|||
typedef void DCC_CONFIG_PTR(DCCMemory *mem, Configuration config, uint32_t value);
|
||||
|
||||
#ifdef CDEFS
|
||||
const char *CFLAGS = "C:DumpNow DCC Loader. (c) 2025 Wrapper.;Compile flags: " CDEFS ";Compile Date: " __DATE__;
|
||||
const char CFLAGS[] = "C:DumpNow DCC Loader. (c) 2025 Wrapper.;Compile flags: " CDEFS ";Compile Date: " __DATE__;
|
||||
#endif
|
||||
|
||||
static uint8_t rawBuf[DCC_BUFFER_SIZE + 0x2000];
|
||||
|
|
@ -18,9 +18,6 @@ static uint8_t compBuf[DCC_BUFFER_SIZE + 0x4000];
|
|||
#endif
|
||||
#ifdef DCC_TESTING
|
||||
extern void DCC_COMPRESS_MEMCPY(uint32_t algo, uint32_t src_offset, uint32_t size);
|
||||
void *absolute_to_relative(void* ptr) { return ptr; };
|
||||
#else
|
||||
extern void *absolute_to_relative(void *ptr);
|
||||
#endif
|
||||
|
||||
size_t strlen(const char *str);
|
||||
|
|
@ -32,7 +29,6 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
uint32_t BUF_INIT[2048];
|
||||
uint32_t dcc_init_offset = 0;
|
||||
uint32_t ext_mem;
|
||||
Driver *devBase;
|
||||
DCC_RETURN res;
|
||||
|
||||
/* 01 - Probe flash devices */
|
||||
|
|
@ -40,8 +36,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
if (!devices[i].driver) break; // Break when reaching the end of list
|
||||
|
||||
/* Probe device */
|
||||
devBase = (Driver *)absolute_to_relative(devices[i].driver);
|
||||
res = ((DCC_INIT_PTR *)absolute_to_relative(devBase->initialize))(&mem[i], devices[i].base_offset);
|
||||
res = devices[i].driver->initialize(&mem[i], devices[i].base_offset);
|
||||
if (res != DCC_OK) mem[i].type = MEMTYPE_NONE;
|
||||
|
||||
/* Print appropriate value */
|
||||
|
|
@ -219,8 +214,7 @@ void dcc_main(uint32_t StartAddress, uint32_t PageSize) {
|
|||
case MEMTYPE_AND:
|
||||
case MEMTYPE_AG_AND:
|
||||
/* Get driver routines */
|
||||
devBase = (Driver *)absolute_to_relative(devices[flashIndex - 1].driver);
|
||||
res = ((DCC_READ_PTR *)absolute_to_relative(devBase->read))(&mem[flashIndex - 1], srcOffset, srcSize, rawBuf, &destSize);
|
||||
res = devices[flashIndex - 1].driver->read(&mem[flashIndex - 1], srcOffset, srcSize, rawBuf, &destSize);
|
||||
if (res != DCC_OK) { // Check if error
|
||||
DN_Packet_Send_One(CMD_READ_RESP_FAIL(res));
|
||||
continue;
|
||||
|
|
|
|||
13
makefile
13
makefile
|
|
@ -130,7 +130,7 @@ else
|
|||
DDEFS += -DUSE_OLD_DCC_IO=0
|
||||
endif
|
||||
|
||||
SRC = main.c dcc/memory.c dcc/dn_dcc_proto.c dcc/bitutils.c dcc/lwprintf.c plat/$(PLATFORM).c devices/$(LOADER_DEVICES).c $(DEVICES) $(CONTROLLERS) $(ADD_DEPS)
|
||||
SRC = main.c dcc/pic.c dcc/memory.c dcc/dn_dcc_proto.c dcc/bitutils.c dcc/lwprintf.c plat/$(PLATFORM).c devices/$(LOADER_DEVICES).c $(DEVICES) $(CONTROLLERS) $(ADD_DEPS)
|
||||
|
||||
# List ASM source files here
|
||||
ASRC = crt.s
|
||||
|
|
@ -160,9 +160,13 @@ OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
|
|||
LIBS = $(DLIBS) $(ULIBS)
|
||||
MCFLAGS = -mcpu=$(MCU)
|
||||
|
||||
ASFLAGS = $(MCFLAGS) -fPIC -fPIE -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -c
|
||||
CPFLAGS = $(MCFLAGS) -fPIC -fPIE -I . $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
LDFLAGS = $(MCFLAGS) -fPIC -fPIE -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
|
||||
ifeq ($(BIG_ENDIAN), 1)
|
||||
MCFLAGS += -mbig-endian -mbe32
|
||||
endif
|
||||
|
||||
ASFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -mgeneral-regs-only -fPIE -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -c
|
||||
CPFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -mgeneral-regs-only -fPIE -I . $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
LDFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -mgeneral-regs-only -fPIE -pie -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
|
||||
|
||||
# Generate dependency information
|
||||
#CPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
|
|
@ -228,6 +232,7 @@ endif
|
|||
$(info PROJECT=(name) = Output name)
|
||||
$(info LDSCRIPT=(ld) = Linker script)
|
||||
$(info OLD_IO=1 = Use old DCC IO routines)
|
||||
$(info BIG_ENDIAN=1 = Big endian format)
|
||||
$(info Flash devices:)
|
||||
$(info CFI=1 = Enable CFI interface)
|
||||
$(info NAND_CONTROLLER=(name) = Enable NAND controller)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue