NO Pic by default
This commit is contained in:
wrapper
parent
8c9e6309db
commit
256c308060
6 changed files with 498 additions and 23 deletions
23
crt.s
23
crt.s
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@ -47,20 +47,23 @@ _vectors:
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.global ResetHandler
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.global ExitFunction
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#if USE_BREAKPOINTS
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.global DN_Packet_DCC_WaitForBP
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.global DCC_PKT_RW_DATA
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.global DCC_PKT_RW_SIZE
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#endif
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#ifndef NO_PIC
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#ifdef PIC
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.extern pic_relocate
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#endif
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.extern dcc_main
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.extern __stack_und_end
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/* Variables */
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StartAddress: .word 0xffffffff
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FlashSize: .word 0x0
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NoAutoSize: .word 0x0
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PageSize: .word 0xffffffff
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/* Loader via H/W BP polling */
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@ -82,10 +85,10 @@ CrashHandler:
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/* DCC info */
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.ascii "DNDL"
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#ifdef NO_PIC
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.word 0
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#else
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#ifdef PIC
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.word 1
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#else
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.word 0
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#endif
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.word _vectors
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.word __bss_start
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@ -124,20 +127,20 @@ ResetHandler:
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#endif
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/* 01 - Initialize stack section */
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#ifndef NO_PIC
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#ifdef PIC
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mov r0, #0
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adr r0, _vectors
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#endif
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ldr sp, =__stack_svc_end
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#ifndef NO_PIC
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#ifdef PIC
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add sp, r0
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#endif
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bl plat_init
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/* 02 - Reset memory */
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#ifndef NO_PIC
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#ifdef PIC
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mov r0, #0
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adr r0, _vectors
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#endif
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@ -149,7 +152,7 @@ ResetHandler:
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ldr r2, =__bss_end
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mov r3, #0
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#ifndef NO_PIC
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#ifdef PIC
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add r1, r0
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add r2, r0
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#endif
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@ -159,7 +162,7 @@ bss_clear_loop:
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bne bss_clear_loop
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/* 03 - Code initialize */
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#ifndef NO_PIC
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#ifdef PIC
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mov r0, #0
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adr r0, _vectors
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@ -40,6 +40,8 @@
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* Open "include/lwprintf/lwprintf_opt.h" and
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* copy & replace here settings you want to change values
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*/
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#define LWPRINTF_CFG_SUPPORT_LONG_LONG 0
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#define LWPRINTF_CFG_SUPPORT_TYPE_FLOAT 0
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#define LWPRINTF_CFG_SUPPORT_TYPE_ENGINEERING 0
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219
flash/nand/controller/emp/db2020.c
Normal file
219
flash/nand/controller/emp/db2020.c
Normal file
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@ -0,0 +1,219 @@
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/* Nand controller template */
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#include "../controller.h"
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#include "dcc/dn_dcc_proto.h"
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#include "dcc/plat.h"
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#include "./db2020.h"
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static uint8_t bits;
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void inline NAND_Ctrl_Command_Write(uint8_t cmd) {
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// Write command routines
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WRITE_U8(0x80010000, cmd);
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wdog_reset();
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}
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void inline NAND_Ctrl_Address_Write(uint8_t addr) {
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// Write address routines
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WRITE_U8(0x80020000, addr);
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wdog_reset();
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}
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void inline DB2xxx_NAND_ReadData(unsigned char *data) {
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int count = 0x10;
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uint32_t temp;
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do {
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do { wdog_reset(); } while (!(READ_U32(NAND_CTRL_BASE + REG_INTERRUPT) & 4));
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for (int i = 0; i < 8; i++) {
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temp = READ_U32(NAND_CTRL_BASE + REG_DATA_READ);
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*data = temp;
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*(data + 1) = temp >> 8;
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*(data + 2) = temp >> 0x10;
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*(data + 3) = temp >> 0x18;
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data += 4;
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}
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WRITE_U32(NAND_CTRL_BASE + REG_INTERRUPT, 0xff);
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count--;
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} while (count);
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}
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void inline DB2xxx_NAND_ReadOOB(unsigned char *oob) {
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uint32_t temp;
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// do { wdog_reset(); } while (!(READ_U32(NAND_CTRL_BASE + REG_INTERRUPT) & 4));
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for (int i = 0; i < 4; i++) {
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temp = READ_U32(NAND_CTRL_BASE + REG_DATA_READ);
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*oob = temp;
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*(oob + 1) = temp >> 8;
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*(oob + 2) = temp >> 0x10;
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*(oob + 3) = temp >> 0x18;
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oob += 4;
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}
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}
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uint16_t inline NAND_Ctrl_Data_Read() {
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// Data read routines
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wdog_reset();
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return bits == 16 ? READ_U16(0x80000000) : READ_U8(0x80000000); // TODO: 32-bit NAND data read
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}
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void inline NAND_Ctrl_Wait_Ready() {
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// Busy assert routines
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do { wdog_reset(); } while (READ_U32(0x9F8000C8) & 2) ;
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}
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uint32_t inline NAND_Ctrl_Check_Status() {
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return 1;
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}
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DCC_RETURN NAND_Ctrl_Probe(DCCMemory *mem) {
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wdog_reset();
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mem->type = MEMTYPE_NONE;
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NAND_Ctrl_Command_Write(NAND_CMD_RESET);
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NAND_Ctrl_Wait_Ready();
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NAND_Ctrl_Command_Write(NAND_CMD_READID);
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NAND_Ctrl_Address_Write(0x0);
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NAND_Ctrl_Wait_Ready();
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uint8_t mfr_id = (uint8_t)NAND_Ctrl_Data_Read();
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uint8_t dev_id = (uint8_t)NAND_Ctrl_Data_Read();
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for (int i = 0; flash_ids[i].dev_id; i++) {
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if (dev_id == (uint8_t)flash_ids[i].dev_id) {
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mem->device_id = dev_id;
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mem->manufacturer = mfr_id;
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mem->bit_width = flash_ids[i].bits;
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mem->block_size = flash_ids[i].block_size;
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mem->page_size = flash_ids[i].page_size;
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mem->size = flash_ids[i].chip_size;
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mem->type = MEMTYPE_NAND;
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break;
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}
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}
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if (mem->type != MEMTYPE_NAND) return DCC_PROBE_ERROR;
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if (mem->page_size == 0) {
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NAND_Ctrl_Data_Read();
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uint8_t extra_id = (uint8_t)NAND_Ctrl_Data_Read();
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mem->page_size = 1 << (10 + (extra_id & 3));
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switch ((extra_id >> 4) & 3) {
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case 0:
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mem->block_size = 64 << 10;
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break;
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case 1:
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mem->block_size = 128 << 10;
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break;
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case 2:
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mem->block_size = 256 << 10;
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break;
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case 3:
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mem->block_size = 512 << 10;
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break;
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}
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mem->device_id |= extra_id << 8;
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}
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bits = mem->bit_width;
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NAND_Ctrl_Command_Write(NAND_CMD_RESET);
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NAND_Ctrl_Wait_Ready();
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return DCC_OK;
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}
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DCC_RETURN NAND_Ctrl_Read(DCCMemory *mem, uint8_t *page_buf, uint8_t *spare_buf, uint32_t page) {
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wdog_reset();
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if (mem->page_size <= 512) {
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NAND_Ctrl_Command_Write(NAND_CMD_READ0);
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NAND_Ctrl_Address_Write(0);
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NAND_Ctrl_Address_Write(page);
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NAND_Ctrl_Address_Write(page >> 8);
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if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
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NAND_Ctrl_Wait_Ready();
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if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
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for (int i = 0; i < 0x100; i++) {
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wdog_reset();
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if (mem->bit_width == 16) {
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((uint16_t *)(page_buf))[i] = NAND_Ctrl_Data_Read();
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} else {
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page_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
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}
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}
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if (mem->bit_width == 8) {
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NAND_Ctrl_Command_Write(NAND_CMD_READ1);
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NAND_Ctrl_Address_Write(0);
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NAND_Ctrl_Address_Write(page);
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NAND_Ctrl_Address_Write(page >> 8);
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if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
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NAND_Ctrl_Wait_Ready();
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if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
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for (int i = 0; i < 0x100; i++) {
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wdog_reset();
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page_buf[i + 0x100] = (uint8_t)NAND_Ctrl_Data_Read();
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}
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}
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NAND_Ctrl_Command_Write(NAND_CMD_READOOB);
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NAND_Ctrl_Address_Write(0);
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NAND_Ctrl_Address_Write(page);
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NAND_Ctrl_Address_Write(page >> 8);
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if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
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NAND_Ctrl_Wait_Ready();
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if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
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for (int i = 0; i < (0x10 >> (mem->bit_width >> 4)); i++) {
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wdog_reset();
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if (mem->bit_width == 16) {
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((uint16_t *)(spare_buf))[i] = NAND_Ctrl_Data_Read();
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} else {
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spare_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
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}
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}
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} else {
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NAND_Ctrl_Command_Write(NAND_CMD_READ0);
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NAND_Ctrl_Address_Write(0);
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NAND_Ctrl_Address_Write(0);
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NAND_Ctrl_Address_Write(page);
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NAND_Ctrl_Address_Write(page >> 8);
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if (mem->size > 0x08000000) NAND_Ctrl_Address_Write(page >> 16);
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NAND_Ctrl_Command_Write(NAND_CMD_READSTART);
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NAND_Ctrl_Wait_Ready();
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if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
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for (int i = 0; i < (mem->page_size >> (mem->bit_width >> 4)); i++) {
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wdog_reset();
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if (mem->bit_width == 16) {
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((uint16_t *)(page_buf))[i] = NAND_Ctrl_Data_Read();
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} else {
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page_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
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}
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}
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for (int i = 0; i < ((mem->page_size >> 5) >> (mem->bit_width >> 4)); i++) {
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wdog_reset();
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if (mem->bit_width == 16) {
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((uint16_t *)(spare_buf))[i] = NAND_Ctrl_Data_Read();
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} else {
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spare_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
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}
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}
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}
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return DCC_OK;
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}
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34
flash/nand/controller/emp/db2020.h
Normal file
34
flash/nand/controller/emp/db2020.h
Normal file
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@ -0,0 +1,34 @@
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#pragma once
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#define NAND_CTRL_BASE 0x24000000
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#define REG_DATA 0x04
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#define REG_ADDR 0x08
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#define REG_CFG 0x10
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#define REG_INTERRUPT 0x18
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#define REG_STATUS 0x1c
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#define REG_CMD 0x20
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#define REG_CMD2 0x24
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#define REG_ALWAYS_ONE 0x50
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#define REG_DATA_READ 0x54
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#define REG_CTRL 0x58
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#define REG_ALWAYS_TWO_01 0x5c
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#define REG_ALWAYS_TWO_02 0x8c
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#define REG_ALWAYS_TWO_03 0x90
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#define VAL_RUN_CFG 0x5603
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#define VAL_IDLE_CFG 0x5703
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#define VAL_CMD_MASK 0xFFFF0000
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#define VAL_READ_DATA_CMD_CTRL 0x80
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#define VAL_READ_OOB_CMD_CTRL 0x4
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#define VAL_READ_ADDR_CTRL 0x4000000
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#define VAL_READ_ADDR_CTRL_MASK 0xffffff
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#define VAL_READ_DATA_CTRL 0x20000
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#define VAL_READ_DATA_CTRL_MASK 0xFFFDFFFF
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#define VAL_INTERRUPT_RESET 0xff
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#define BIT_INTERRUPT_READY 0x4
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#define BIT_STATUS_READY 0x1
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216
flash/nand/controller/qcom/niche/ascot.c
Normal file
216
flash/nand/controller/qcom/niche/ascot.c
Normal file
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/* Nand controller template */
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#include "../../controller.h"
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#include "dcc/dn_dcc_proto.h"
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#include "dcc/plat.h"
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static uint16_t tempvar;
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#define ASCOT_CTRL 0x0298030C
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void inline ASCOT_SetFunction(uint8_t data, uint16_t set, uint16_t bitmask)
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{
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WRITE_U16(data, (tempvar & ~set) | (set & bitmask));
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tempvar = (tempvar & ~set) | (set & bitmask);
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}
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void inline ASCOT_SetFunction_NoTemp(uint8_t data, uint16_t set, uint16_t bitmask)
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{
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// *offset = *offset & ~set | set & bitmask;
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WRITE_U16(data, (READ_U16(data) & ~set) | (set & bitmask));
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}
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void inline ASCOT_SetBitMask(uint32_t offset, uint16_t set, uint16_t bitmask)
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{
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WRITE_U16(offset, (READ_U16(offset) & ~set) | (set & bitmask));
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}
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void inline ASCOT_SetBitMask_Temp(uint32_t offset, uint16_t set, uint16_t bitmask)
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{
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WRITE_U16(offset, (READ_U16(offset) & ~set) | (set & bitmask));
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}
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void inline ASCOT_Open(int index) {
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ASCOT_SetBitMask(ASCOT_CTRL, 1, 1);
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}
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void inline NAND_Ctrl_Command_Write(uint8_t cmd) {
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// Write command routines
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wdog_reset();
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// GPIO 29
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MSM5100_GPIO_Write(29, 1);
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WRITE_U16(0x00800000, cmd);
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MSM5100_GPIO_Write(29, 0);
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}
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void inline NAND_Ctrl_Address_Write(uint8_t addr) {
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// Write address routines
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wdog_reset();
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// GPIO 28
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MSM5100_GPIO_Write(28, 1);
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WRITE_U16(0x00800000, addr);
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MSM5100_GPIO_Write(28, 0);
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}
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uint16_t inline NAND_Ctrl_Data_Read() {
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// Data read routines
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wdog_reset();
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return READ_U16(0x00800000);
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}
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void inline NAND_Ctrl_Wait_Ready() {
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// Busy assert routines
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// GPIO 6
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do { wdog_reset(); } while ( !MSM5100_GPIO_Read(6) );
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}
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uint32_t inline NAND_Ctrl_Check_Status() {
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return 1;
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}
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DCC_RETURN NAND_Ctrl_Probe(DCCMemory *mem) {
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wdog_reset();
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mem->type = MEMTYPE_NONE;
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NAND_Ctrl_Command_Write(NAND_CMD_RESET);
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NAND_Ctrl_Wait_Ready();
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NAND_Ctrl_Command_Write(NAND_CMD_READID);
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NAND_Ctrl_Address_Write(0x0);
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NAND_Ctrl_Wait_Ready();
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uint8_t mfr_id = (uint8_t)NAND_Ctrl_Data_Read();
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uint8_t dev_id = (uint8_t)NAND_Ctrl_Data_Read();
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for (int i = 0; flash_ids[i].dev_id; i++) {
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if (dev_id == (uint8_t)flash_ids[i].dev_id) {
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mem->device_id = dev_id;
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mem->manufacturer = mfr_id;
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mem->bit_width = flash_ids[i].bits;
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mem->block_size = flash_ids[i].block_size;
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mem->page_size = flash_ids[i].page_size;
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mem->size = flash_ids[i].chip_size;
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mem->type = MEMTYPE_NAND;
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break;
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}
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}
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if (mem->type != MEMTYPE_NAND) return DCC_PROBE_ERROR;
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if (mem->page_size == 0) {
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NAND_Ctrl_Data_Read();
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uint8_t extra_id = (uint8_t)NAND_Ctrl_Data_Read();
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mem->page_size = 1 << (10 + (extra_id & 3));
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switch ((extra_id >> 4) & 3) {
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case 0:
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mem->block_size = 64 << 10;
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break;
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case 1:
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mem->block_size = 128 << 10;
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break;
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case 2:
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mem->block_size = 256 << 10;
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break;
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case 3:
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mem->block_size = 512 << 10;
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break;
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}
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|
||||
mem->device_id |= extra_id << 8;
|
||||
}
|
||||
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_RESET);
|
||||
NAND_Ctrl_Wait_Ready();
|
||||
return DCC_OK;
|
||||
}
|
||||
|
||||
DCC_RETURN NAND_Ctrl_Read(DCCMemory *mem, uint8_t *page_buf, uint8_t *spare_buf, uint32_t page) {
|
||||
wdog_reset();
|
||||
|
||||
if (mem->page_size <= 512) {
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_READ0);
|
||||
NAND_Ctrl_Address_Write(0);
|
||||
NAND_Ctrl_Address_Write(page);
|
||||
NAND_Ctrl_Address_Write(page >> 8);
|
||||
if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
|
||||
|
||||
NAND_Ctrl_Wait_Ready();
|
||||
if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
|
||||
|
||||
for (int i = 0; i < 0x100; i++) {
|
||||
wdog_reset();
|
||||
if (mem->bit_width == 16) {
|
||||
((uint16_t *)(page_buf))[i] = NAND_Ctrl_Data_Read();
|
||||
} else {
|
||||
page_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
|
||||
}
|
||||
}
|
||||
|
||||
if (mem->bit_width == 8) {
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_READ1);
|
||||
NAND_Ctrl_Address_Write(0);
|
||||
NAND_Ctrl_Address_Write(page);
|
||||
NAND_Ctrl_Address_Write(page >> 8);
|
||||
if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
|
||||
|
||||
NAND_Ctrl_Wait_Ready();
|
||||
if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
|
||||
|
||||
for (int i = 0; i < 0x100; i++) {
|
||||
wdog_reset();
|
||||
page_buf[i + 0x100] = (uint8_t)NAND_Ctrl_Data_Read();
|
||||
}
|
||||
}
|
||||
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_READOOB);
|
||||
NAND_Ctrl_Address_Write(0);
|
||||
NAND_Ctrl_Address_Write(page);
|
||||
NAND_Ctrl_Address_Write(page >> 8);
|
||||
if (mem->size > 0x02000000) NAND_Ctrl_Address_Write(page >> 16);
|
||||
|
||||
NAND_Ctrl_Wait_Ready();
|
||||
if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
|
||||
|
||||
for (int i = 0; i < (0x10 >> (mem->bit_width >> 4)); i++) {
|
||||
wdog_reset();
|
||||
if (mem->bit_width == 16) {
|
||||
((uint16_t *)(spare_buf))[i] = NAND_Ctrl_Data_Read();
|
||||
} else {
|
||||
spare_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
|
||||
}
|
||||
}
|
||||
} else {
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_READ0);
|
||||
NAND_Ctrl_Address_Write(0);
|
||||
NAND_Ctrl_Address_Write(0);
|
||||
NAND_Ctrl_Address_Write(page);
|
||||
NAND_Ctrl_Address_Write(page >> 8);
|
||||
if (mem->size > 0x08000000) NAND_Ctrl_Address_Write(page >> 16);
|
||||
|
||||
NAND_Ctrl_Command_Write(NAND_CMD_READSTART);
|
||||
NAND_Ctrl_Wait_Ready();
|
||||
if (!NAND_Ctrl_Check_Status()) return DCC_READ_ERROR;
|
||||
|
||||
for (int i = 0; i < (mem->page_size >> (mem->bit_width >> 4)); i++) {
|
||||
wdog_reset();
|
||||
if (mem->bit_width == 16) {
|
||||
((uint16_t *)(page_buf))[i] = NAND_Ctrl_Data_Read();
|
||||
} else {
|
||||
page_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < ((mem->page_size >> 5) >> (mem->bit_width >> 4)); i++) {
|
||||
wdog_reset();
|
||||
if (mem->bit_width == 16) {
|
||||
((uint16_t *)(spare_buf))[i] = NAND_Ctrl_Data_Read();
|
||||
} else {
|
||||
spare_buf[i] = (uint8_t)NAND_Ctrl_Data_Read();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return DCC_OK;
|
||||
}
|
||||
27
makefile
27
makefile
|
|
@ -110,9 +110,8 @@ ifeq ($(NO_COMPRESS), 1)
|
|||
DDEFS += -DDISABLE_COMPRESS=1
|
||||
endif
|
||||
|
||||
ifeq ($(NO_PIC), 1)
|
||||
DADEFS += -DNO_PIC
|
||||
else
|
||||
ifeq ($(PIC), 1)
|
||||
DADEFS += -DUSE_PIC
|
||||
ADD_DEPS += dcc/pic.c
|
||||
endif
|
||||
|
||||
|
|
@ -145,21 +144,24 @@ ADEFS = $(DADEFS) $(UADEFS) -DADEFS="\"FLAGS=$(DADEFS) $(UADEFS) CPU=$(MCU)\""
|
|||
OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
|
||||
LIBS = $(DLIBS) $(ULIBS)
|
||||
MCFLAGS = -mcpu=$(MCU)
|
||||
CC_PIC =
|
||||
AS_PIC =
|
||||
|
||||
ifeq ($(BIG_ENDIAN), 1)
|
||||
MCFLAGS += -mbig-endian -mbe32
|
||||
endif
|
||||
|
||||
ifeq ($(NO_PIC), 1)
|
||||
ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -c
|
||||
CPFLAGS = $(MCFLAGS) -I . $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
|
||||
else
|
||||
ASFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -fPIE -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -c
|
||||
CPFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -fPIE -I . $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
LDFLAGS = $(MCFLAGS) -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -fPIE -pie -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
|
||||
ifeq ($(PIC), 1)
|
||||
CC_PIC += -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -fPIE
|
||||
AS_PIC += -fPIC -mpic-register=r9 -mpic-data-is-text-relative -msingle-pic-base -fPIE -pie
|
||||
endif
|
||||
|
||||
ASFLAGS = $(MCFLAGS) $(CC_PIC) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -c
|
||||
#CPFLAGS = $(MCFLAGS) $(CC_PIC) -I . $(OPT) -g -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
CPFLAGS = $(MCFLAGS) $(CC_PIC) -I . $(OPT) -g -gdwarf-2 -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -c
|
||||
LDFLAGS = $(MCFLAGS) $(AS_PIC) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=build/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
|
||||
|
||||
|
||||
# Generate dependency information
|
||||
#CPFLAGS += -MD -MP -MF .dep/$(@F).d
|
||||
|
||||
|
|
@ -222,10 +224,9 @@ endif
|
|||
$(info $(NULL) BUFFER_SIZE=(Buffer Size) = DCC Buffer Size (Default: 0x40000))
|
||||
$(info $(NULL) PROJECT=(name) = Output name)
|
||||
$(info $(NULL) LDSCRIPT=(ld) = Linker script)
|
||||
$(info $(NULL) NEW_IO=1 = Use new DCC IO routines, RLE currently doesn't work in RIFF)
|
||||
$(info $(NULL) NO_COMPRESS=1 = Disable RLE compression, used if using with RIFF says failed to unpack received data.)
|
||||
$(info $(NULL) BIG_ENDIAN=1 = Big endian format)
|
||||
$(info $(NULL) NO_PIC=1 = Disable PIC support)
|
||||
$(info $(NULL) PIC=1 = Use PIC code)
|
||||
$(info Flash devices:)
|
||||
$(info $(NULL) CFI=1 = Enable CFI interface)
|
||||
$(info $(NULL) NAND_CONTROLLER=(name) = Enable NAND controller)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue